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6070a?atarm?28-oct-04 features incorporates the arm7tdmi ? arm ? thumb ? processor ? high-performance 32-bit risc architecture ? high-density 16-bit instruction set ? leader in mips/watt ? embedded ice in-circuit emulation, debug communication channel support 64 kbytes of internal high-speed flash, organized in 512 pages of 128 bytes ? single cycle access at up to 30 mhz in worst case conditions, prefetch buffer optimizing thumb instruction execution at maximum speed ? page programming time: 4 ms, including page auto-erase, full erase time: 10 ms ? 10,000 write cycles, 10-year data retention capability, sector lock capabilities, flash security bit ? fast flash programming interface for high volume production 16 kbytes of internal high-speed sram, single-cycle access at maximum speed memory controller (mc) ? embedded flash controller, abort status and misalignment detection reset controller (rstc) ? based on power-on reset and low-power factory-calibrated brownout detector ? provides external reset signal shaping and reset source status clock generator (ckgr) ? low-power rc oscillator, 3 to 20 mhz on-chip oscillator and one pll power management controller (pmc) ? software power optimization capabilities, including slow clock mode (down to 500 hz) and idle mode ? three programmable external clock signals advanced interrupt controller (aic) ? individually maskable, eight-level priority, vectored interrupt sources ? two external interrupt sources and one fast interrupt source, spurious interrupt protected debug unit (dbgu) ? 2-wire uart and support for debug communication channel interrupt, programmable ice access prevention periodic interval timer (pit) ? 20-bit programmable counter plus 12-bit interval counter windowed watchdog (wdt) ? 12-bit key-protected programmable counter ? provides reset or interrupt signals to the system ? counter may be stopped while the processor is in debug state or in idle mode real-time timer (rtt) ? 32-bit free-running counter with alarm ? runs off the internal rc oscillator one parallel input/output controller (pioa) ? thirty-two programmable i/o lines multiplexed with up to two peripheral i/os ? input change interrupt capability on each i/o line ? individually programmable open-drain, pull-up resistor and synchronous output eleven peripheral data controller (pdc) channels one usb 2.0 full speed (12 mbits per second) device port ? on-chip transceiver, 328-byte configurable integrated fifos one synchronous serial controller (ssc) ? independent clock and frame sync signals for each receiver and transmitter ? i2s analog interface support, time division multiplex support ? high-speed continuous data stream capabilities with 32-bit data transfer two universal synchronous/asynchronous receiver transmitters (usart) ? individual baud rate generator, irda infrared modulation/demodulation ? support for iso7816 t0/t1 smart card, hardware handshaking, rs485 support ? full modem line support on usart1 one master/slave serial peripheral interface (spi) ? 8- to 16-bit programmable data length, four external peripheral chip selects at91 arm ? thumb ? -based microcontrollers at91sam7s64 preliminary
2 at91sam7s64 preliminary 6070a?atarm?28-oct-04 one three-channel 16-bit timer/counter (tc) ? three external clock inputs, two multi-purpose i/o pins per channel ? double pwm generation, capture/waveform mode, up/down capability one four-channel 16-bit pwm controller (pwmc) one two-wire interface (twi) ? master mode support only, all two-wire atmel eeproms supported one 8-channel 10-bit analog-to-digital converter, four channels multiplexed with digital i/os ieee 1149.1 jtag boundary scan on all digital pins 5v-tolerant i/os, including four high-current drive i/o lines, up to 16 ma each power supplies ? embedded 1.8v regulator, drawing up to 100 ma for the core and external components ? 3.3v vddio i/o lines power supply, independent 3.3v vddflash flash power supply ? 1.8v vddcore core power supply with brownout detector fully static operation: up to 55 mhz at 1.65v and 85c worst case conditions available in a 64-lead lqfp package description atmel?s at91sam7s64 is a member of a series of low pincount flash microcontrollers based on the 32-bit arm risc processor. it features a 64 kbyte high-speed flash and a 16 kbyte sram, a large set of peripherals, including a usb 2.0 device, and a com- plete set of system functions minimizing the number of external components. the device is an ideal migration path for 8-bit microcontroller users looking for additional per- formance and extended memory. the embedded flash memory can be programmed in-system via the jtag-ice inter- face or via a parallel interface on a production programmer prior to mounting. built-in lock bits and a security bit protect the firmware from accidental overwrite and preserves its confidentiality. the at91sam7s64 system controller includes a reset controller capable of managing the power-on sequence of the microcontrolle r and the complete system. correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated rc oscillator. the at91sam7s64 is a general-purpose microcontroller. its integrated usb device port makes it an ideal device for peripheral applications requiring connectivity to a pc or cellular phone. its aggressive price point and high level of integration pushes its scope of use far into the cost-sensitive, high-volume consumer market.
3 at91sam7s64 preliminary 6070a?atarm?28-oct-04 block diagram figure 1. at91sam7s64 block diagram tdi tdo tms tck nrst fiq irq0-irq1 pck0-pck2 pmc peripheral bridge peripheral data controller aic pll rcosc sram 16 kbytes arm7tdmi processor ice jtag scan jtagsel pioa usart0 ssc timer counter rxd0 txd0 sck0 rts0 cts0 npcs0 npcs1 npcs2 npcs3 miso mosi spck flash 64 kbytes reset controller drxd dtxd tf tk td rd rk rf tclk0 tclk1 tclk2 tioa0 tiob0 tioa1 tiob1 tioa2 tiob2 memory controller abort status address decoder misalignment detection pio pio apb por embedded flash controller ad0 ad1 ad2 ad3 adtrg pllrc 11 channels pdc pdc usart1 rxd1 txd1 sck1 rts1 cts1 dcd1 dsr1 dtr1 ri1 pdc pdc pdc pdc spi pdc adc advref pdc pdc tc0 tc1 tc2 twd twck twi osc xin xout vddin pwmc pwm0 pwm1 pwm2 pwm3 1.8 v voltage regulator usb device fifo ddm ddp transceiver gnd vddout bod vddcore vddcore ad4 ad5 ad6 ad7 vddflash fast flash programming interface erase pio pgmd0-pgmd15 pgmncmd pgmen0-pgmen1 pgmrdy pgmnvalid pgmnoe pgmck pgmm0-pgmm3 vddio tst dbgu pdc pdc pio pit wdt rtt system controller vddcore
4 at91sam7s64 preliminary 6070a?atarm?28-oct-04 signal description table 1. signal description list signal name function type active level comments power vddin voltage regulator power supply input power 3.0v to 3.6v vddout voltage regulator output power 1.85v nominal vddflash flash power supply power 3.0v to 3.6v vddio i/o lines power supply power 3.0v to 3.6v vddcore core power supply power 1.65v to 1.95v vddpll pll power 1.65v to 1.95v gnd ground ground clocks, oscillators and plls xin main oscillator input input xout main oscillator output output pllrc pll filter input pck0 - pck2 programmable clock output output ice and jtag tck test clock input no pull-up resistor tdi test data in input no pull-up resistor tdo test data out output tms test mode select input no pull-up resistor jtagsel jtag selection input pull-down resistor flash memory erase flash and nvm configuration bits erase command input high pull-down resistor reset/test nrst microcontroller reset i/o low pull-up resistor tst test mode select input pull-down resistor debug unit drxd debug receive data input dtxd debug transmit data output aic irq0 - irq1 external interrupt inputs input fiq fast interrupt input input
5 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pio pa0 - pa31 parallel io controller a i/o pulled-up input at reset usb device port ddm usb device port data - analog ddp usb device port data + analog usart sck0 - sck1 serial clock i/o txd0 - txd1 transmit data i/o rxd0 - rxd1 receive data input rts0 - rts1 request to send output cts0 - cts1 clear to send input dcd1 data carrier detect input dtr1 data terminal ready output dsr1 data set ready input ri1 ring indicator input synchronous serial controller td transmit data output rd receive data input tk transmit clock i/o rk receive clock i/o tf transmit frame sync i/o rf receive frame sync i/o timer/counter tclk0 - tclk2 external clock inputs input tioa0 - tioa2 i/o line a i/o tiob0 - tiob2 i/o line b i/o pwm controller pwm0 - pwm3 pwm channels output spi miso master in slave out i/o mosi master out slave in i/o spck spi serial clock i/o npcs0 spi peripheral chip select 0 i/o low npcs1-npcs3 spi peripheral chip select 1 to 3 output low table 1. signal description list (continued) signal name function type active level comments
6 at91sam7s64 preliminary 6070a?atarm?28-oct-04 two-wire interface twd two-wire serial data i/o twck two-wire serial clock i/o analog-to-digital converter ad0-ad3 analog inputs analog digital pulled-up inputs at reset ad4-ad7 analog inputs analog analog inputs adtrg adc trigger input advref adc reference analog fast flash programming interface pgmen0-pgmen1 programming enabling input pgmm0-pgmm3 programming mode input pgmd0-pgmd15 programming data i/o pgmrdy programming ready output high pgmnvalid data direction output low pgmnoe programming read input low pgmck programming clock input pgmncmd programming command input low table 1. signal description list (continued) signal name function type active level comments
7 at91sam7s64 preliminary 6070a?atarm?28-oct-04 package and pinout the at91sam7s64 is available in a 64-lead lqfp package. 64-lead lqfp mechanical overview figure 2 shows the orientation of the 64-lead lqfp package. a detailed mechanical description is given in the section mechanical characteristics of the full datasheet. figure 2. 64-lead lqfp package pinout (top view) pinout 33 49 48 32 17 16 1 64 table 2. at91sam7s64 pinout in 64-lead lqf package 1 advref 17 gnd 33 tdi 49 tdo 2 gnd 18 vddio 34 pa6/pgmnoe 50 jtagsel 3 ad4 19 pa16/pgmd4 35 pa5/pgmrdy 51 tms 4 ad5 20 pa15/pgm3 36 pa4/pgmncmd 52 pa31 5 ad6 21 pa14/pgmd2 37 pa27/pgmd15 53 tck 6 ad7 22 pa13/pgmd1 38 pa28 54 vddcore 7 vddin 23 pa24/pgmd12 39 nrst 55 erase 8 vddout 24 vddcore 40 tst 56 ddm 9 pa17/pgmd5/ad0 25 pa25/pgmd13 41 pa29 57 ddp 10 pa18/pgmd6/ad1 26 pa26/pgmd14 42 pa30 58 vddio 11 pa21/pgmd9 27 pa12/pgmd0 43 pa3 59 vddflash 12 vddcore 28 pa11/pgmm3 44 pa2 60 gnd 13 pa19/pgmd7/ad2 29 pa10/pgmm2 45 vddio 61 xout 14 pa22/pgmd10 30 pa9/pgmm1 46 gnd 62 xin/pgmck 15 pa23/pgmd11 31 pa8/pgmm0 47 pa1/pgmen1 63 pllrc 16 pa20/pgmd8/ad3 32 pa7/pgmnvalid 48 pa0/pgmen0 64 vddpll
8 at91sam7s64 preliminary 6070a?atarm?28-oct-04 power considerations power supplies the at91sam7s64 has six types of power supply pins and integrates a voltage regula- tor, allowing the device to be supplied with only one voltage. the six power supply pin types are: vddin pin. it powers the voltage regulator; voltage ranges from 3.0v to 3.6v, 3.3v nominal. if the voltage regulator is not used, vddin should be connected to gnd. vddout pin. it is the output of the 1.8v voltage regulator. vddio pin. it powers the i/o lines and the usb transceivers; dual voltage range is supported. ranges from 3.0v to 3.6v, 3.3v nominal. vddflash pin. it powers a part of the flash and is required for the flash to operate correctly; voltage ranges from 3.0v to 3.6v, 3.3v nominal. vddcore pins. they power the logic of the device; voltage ranges from 1.65v to 1.95v, 1.8v typical. it can be connected to the vddout pin with decoupling capacitor. vddcore is required for the device, including its embedded flash, to operate correctly. vddpll pin. it powers the oscillator and th e pll. it can be connected directly to the vddout pin. no separate ground pins are provided for the different power supplies. only gnd pins are provided and should be connected as shortly as possible to the system ground plane. power consumption the at91sam7s64 has a static current of less than 60 a on vddcore at 25c, including the rc oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. activating the brownout detector adds 20 a static current. the dynamic power consumption on vddcore is less than 50 ma at full speed when running out of the flash. under the same conditions, the power consumption on vddflash does not exceed 10 ma. voltage regulator the at91sam7s64 embeds a voltage regulator that is managed by the system controller. in normal mode, the voltage regulator consumes less than 100 a static current and draws 100 ma of output current. the voltage regulator also has a low-power mode. in this mode, it consumes less than 20 a static current and draws 1 ma of output current. adequate output supply decoupling is mandatory for vddout to reduce ripple and avoid oscillations. the best way to achieve this is to use two capacitors in parallel: one external 470 pf (or 1 nf) npo capacitor must be connected between vddout and gnd as close to the chip as possible. one external 2.2 f (or 3.3 f) x7r capacitor must be connected between vddout and gnd. adequate input supply decoupling is mandatory for vddin in order to improve startup stability and reduce source voltage drop. the input decoupling capacitor should be placed close to the chip. for example, two capacitors can be used in parallel: 100 nf npo and 4.7 f x7r.
9 at91sam7s64 preliminary 6070a?atarm?28-oct-04 typical powering schematics 3.3v single supply the at91sam7s64 supports a 3.3v single supply mode. the internal regulator is con- nected to the 3.3v source and its output feeds vddcore and the vddpll. figure 3 shows the power schematics to be used for usb bus-powered systems. figure 3. 3.3v system single power supply schematic power source ranges from 4.5v (usb) to 18v 3.3v vddin voltage regulator vddout vddio dc/dc converter vddcore vddflash vddpll
10 at91sam7s64 preliminary 6070a?atarm?28-oct-04 i/o lines considerations jtag port pins tms, tdi and tck are schmitt trigger inputs. tms and tck are 5-v tolerant, tdi is not. tms, tdi and tck do not integrate a pull-up resistor. tdo is an output, driven at up to vddio, and has no pull-up resistor. the pin jtagsel is used to select the jtag boundary scan when asserted at a high level. the pin jtagsel integrates a permanent pull-down resistor of about 15 kw to gnd, so that it can be left unconnected for normal operations. test pin the pin tst is used for manufacturing test or fast programming mode of the at91sam7s64 when asserted high. the pin tst integrates a permanent pull-down resistor of about 15 kw to gnd, so that it can be left unconnected for normal operations. to enter fast programming mode, the tst pin and the pa0 and pa1 pins should be both tied high. driving the tst pin at a high level while pa0 or pa1 is driven at 0 leads to unpredictable results. reset pin the pin nrst is bidirectional. it is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low exter- nally to reset the microcontroller. there is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length. this allows connection of a simple push-button on the pin nrst as system user rese t, and the use of the signal nrst to reset all the components of the system. the pin nrst integrates a permanent pull-up resistor to vddio. erase pin the pin erase is used to re-initialize the flash content and some of its nvm bits. it integrates a permanent pull-down resistor of about 15 kw to gnd, so that it can be left unconnected for normal operations. pio controller a lines all the i/o lines pa0 to pa31 are 5v-tolerant and all integrate a programmable pull-up resistor. programming of this pull-up resistor is performed independently for each i/o line through the pio controllers. 5v-tolerant means that the i/o lines can drive voltage level according to vddio, but can be driven with a voltage of up to 5.5v. however, driving an i/o line with a voltage over vddio while the programmable pull-up resistor is enabled can lead to unpredictable results. care should be taken, in particular at reset, as all the i/o lines default to input with pull-up resistor enabled at reset. i/o line drive levels the pio lines pa0 to pa3 are high-drive current capable. each of these i/o lines can drive up to 16 ma permanently. the remaining i/o lines can draw only 8 ma. however, the total current drawn by all the i/o lines cannot exceed 150 ma.
11 at91sam7s64 preliminary 6070a?atarm?28-oct-04 processor and architecture arm7tdmi processor risc processor based on armv4t von neumann architecture ? runs at up to 55 mhz, providing 0.9 mips/mhz two instruction sets ?arm ? high-performance 32-bit instruction set ? thumb ? high code density 16-bit instruction set three-stage pipeline architecture ? instruction fetch (f) ? instruction decode (d) ? execute (e) debug and test features integrated embedded in-circuit emulator ? two watchpoint units ? test access port accessible through a jtag protocol ? debug communication channel debug unit ? two-pin uart ? debug communication channel interrupt handling ? chip id register ieee1 149.1 jtag boundary-scan on all digital pins memory controller bus arbiter ? handles requests from the arm7tdmi and the peripheral data controller address decoder provides selection signals for ? three internal 1 mbyte memory areas ? one 256 mbyte embedded peripheral area abort status registers ? source, type and all parameters of the access leading to an abort are saved ? facilitates debug by detection of bad pointers misalignment detector ? alignment checking of all data accesses ? abort generation in case of misalignment remap command ? remaps the sram in place of the embedded non-volatile memory ? allows handling of dynamic exception vectors embedded flash controller ? embedded flash interface, up to three programmable wait states ? prefetch buffer, bufferizing and anticipating the 16-bit requests, reducing the required wait states ? key-protected program, erase and lock/unlock sequencer ? single command for erasing, programming and locking operations ? interrupt generation in case of forbidden operation
12 at91sam7s64 preliminary 6070a?atarm?28-oct-04 peripheral data controller handles data transfer between peripherals and memories eleven channels ? two for each usart ? two for the debug unit ? two for the serial synchronous controller ? two for the serial peripheral interface ? one for the analog-to-digital converter low bus arbitration overhead ? one master clock cycle needed for a transfer from memory to peripheral ? two master clock cycles needed for a transfer from peripheral to memory next pointer management for reducing interrupt latency requirements
13 at91sam7s64 preliminary 6070a?atarm?28-oct-04 memory 64 kbytes of flash memory ? 512 pages of 128 bytes ? fast access time, 30 mhz single-cycle access in worst case conditions ? page programming time: 4 ms, including page auto-erase ? page programming without auto-erase: 2 ms ? full chip erase time: 10 ms ? 10,000 write cycles, 10-year data retention capability ? 16 lock bits, each protecting 16 sectors of 32 pages ? protection mode to secure contents of the flash 16 kbytes of fast sram ? single-cycle access at full speed memory mapping internal sram the at91sam7s64 embeds a high-speed 16-kbyte sram bank. after reset and until the remap command is performed, the sram is only accessible at address 0x0020 0000. after remap, the sram also becomes available at address 0x0. internal flash the at91sam7s64 features one bank of 64 kbytes of flash. at any time, the flash is mapped to address 0x0010 0000. it is also accessible at address 0x0 after the reset and before the remap command. figure 4. internal memory mapping 256m bytes flash before remap sram after remap undefined areas (abort) 0x000f ffff 0x001f ffff 0x002f ffff 0x0fff ffff 1 m bytes 1 m bytes 1 m bytes 253 m bytes internal flash internal sram 0x0000 0000 0x0010 0000 0x0020 0000 0x0030 0000
14 at91sam7s64 preliminary 6070a?atarm?28-oct-04 embedded flash flash overview the flash of the at91sam7s64 is organized in 512 pages of 128 bytes. the 65,536 bytes are organized in 32-bit words. the flash contains a 128-byte write buffer, accessible through a 32-bit interface. the flash benefits from the integration of a power reset cell and from the brownout detector. this prevents code corruption during power supply changes, even in the worst conditions. embedded flash controller the embedded flash controller (efc) manages accesses performed by the masters of the system. it enables reading the flash and writing the write buffer. it also contains a user interface, mapped within the memory controller on the apb. the user interface allows: programming of the access parameters of the flash (number of wait states, timings, etc.) starting commands such as full erase, page erase, page program, nvm bit set, nvm bit clear, etc. getting the end status of the last command getting error status programming interrupts on the end of the last commands or on errors the embedded flash controller also provides a dual 32-bit prefetch buffer that opti- mizes 16-bit access to the flash. this is particularly efficient when the processor is running in thumb mode. lock regions the embedded flash controller manages 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. the at91sam7s64 con- tains 16 lock regions and each lock region contains 32 pages of 128 bytes. each lock region has a size of 4 kbytes. if a locked-regions erase or program command occurs, the command is aborted and the efc trigs an interrupt. the 16 nvm bits are software programmable through the efc user interface. the com- mand "set lock bit" enables the protection . the command "clear lock bit" unlocks the lock region. asserting the erase pin clears the lock bits, thus unlocking the entire flash. security bit feature the at91sam7s64 features a security bit, based on a specific nvm-bit. when the security is enabled, any access to the flash, either through the ice interface or through the fast flash programming interface, is forbidden. this ensures the confidentiality of the code programmed in the flash. this security bit can only be enabled, through the command "set security bit" of the efc user interface. disabling the security bit can only be achieved by asserting the erase pin at 1, and after a full flash erase is performed. when the security bit is deac- tivated, all accesses to the flash are permitted. it is important to note that the assertion of the erase pin s hould always be longer than 50 ms. as the erase pin integrates a permanent pull-down, it can be left unconnected during normal operation. however, it is safer to connect it directly to gnd for the final application.
15 at91sam7s64 preliminary 6070a?atarm?28-oct-04 non-volatile brownout detector control two general purpose nvm (gpnvm) bits are used for contro lling the brownout detector (bod), so that even after a power loss, the brownout detector operations remain as defined by the user. these two gpnvm bits can be cleared or set respectively through the commands "clear general-purpose nvm bit" and "set general-purpose nvm bit" of the efc user interface. gpnvm bit 0 is used as a brownout detector enable bit. setting the gpnvm bit 0 enables the bod, clearing it disables the bod. asserting erase clears the gpnvm bit 0 and thus disables the brownout detector by default. the gpnvm bit 1 is used as a brownout reset enable signal for the reset controller. setting the gpnvm bit 1 enables the brownout reset when a brownout is detected, clearing the gpnvm bit 1 disables the brownout reset. asserting er ase disables the brownout reset by default. calibration bits eight nvm bits are used to calibrate the brownout detector and the voltage regulator. these bits are factory configured and cannot be changed by the user. the er ase pin has no effect on the calibration bits. fast flash programming interface the fast flash programming interface allows programming the device through either a serial jtag interface or through a multiplexed fully-handshaked parallel port. it allows gang-programming with market-standard industrial programmers. the ffpi supports read, page program, page er ase, full erase, lock, unlock and protect commands. the fast flash programming interface is enabled and the fast programming mode is entered when the tst pin and the pa0 and pa1 pins are all tied high.
16 at91sam7s64 preliminary 6070a?atarm?28-oct-04 system controller the system controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. figure 5. system controller block diagram nrst slck advanced interrupt controller real-time timer periodic interval timer reset controller pa0-pa31 periph_nreset system controller watchdog timer wdt_fault wdrproc pio controller por bod rcosc gpnvm[0] cal en power management controller osc pll xin xout pllrc mainck pllck pit_irq mck proc_nreset wdt_irq periph_irq{2] periph_nreset periph_clk[2..14] pck mck pmc_irq udpck nirq nfiq rtt_irq embedded peripherals periph_clk[2] pck[0-2] in out enable arm7tdmi slck slck irq0-irq1 fiq irq0-irq1 fiq periph_irq[4..14] periph_irq[2..14] int int periph_nreset periph_clk[4..14] embedded flash flash_poe jtag_nreset flash_poe gpnvm[0..1] flash_wrdis flash_wrdis proc_nreset periph_nreset dbgu_txd dbgu_rxd pit_irq rtt_irq dbgu_irq pmc_irq rstc_irq wdt_irq rstc_irq slck gpnvm[1] boundary scan tap controller jtag_nreset ice_nreset debug pck debug idle debug memory controller mck proc_nreset bod_rst_en proc_nreset periph_nreset periph_nreset idle debug unit dbgu_irq mck dbgu_rxd periph_nreset force_ntrst dbgu_txd usb device port udpck periph_nreset periph_clk[11] periph_irq[11] usb_suspend usb_suspend voltage regulator standby voltage regulator mode controller security_bit cal ice_nreset force_ntrst cal
17 at91sam7s64 preliminary 6070a?atarm?28-oct-04 system controller mapping the system controller peripherals are all mapped to the highest 4 kbytes of address space, between addresses 0xffff f000 and 0xffff ffff. figure 6 shows the mapping of the system controller. note that the memory controller configuration user interface is also mapped within this address space. figure 6. system controller mapping 0xffff f000 0xffff f200 0xffff f1ff 0xffff f3ff 0xffff f5ff 0xffff fbff 0xffff fcff 0xffff feff 0xffff ffff 0xffff f400 0xffff f600 0xffff fc00 0xffff fd0f 0xffff fc2f 0xffff fc3f 0xffff fd4f 0xffff fc6f aic dbgu pioa reserved pmc mc advanced interrupt controller debug unit pio controller a power management controller memory controller 0xffff fd00 0xffff ff00 rstc pit rtt wdt vreg reserved reserved reserved 0xffff fd20 0xffff fd30 0xffff fd40 0xffff fd60 0xffff fd70 reset controller real-time timer periodic interval timer watchdog timer voltage regulator mode controller 512 bytes/128 registers 512 bytes/128 registers 512 bytes/128 registers 256 bytes/64 registers 16 bytes/4 registers 16 bytes/4 registers 16 bytes/4 registers 16 bytes/4 registers 256 bytes/64 registers 4 bytes/1 register peripheral name size address peripheral
18 at91sam7s64 preliminary 6070a?atarm?28-oct-04 reset controller the reset controller is based on a power-on reset cell and one brownout detector. it gives the status of the last reset, indicating whether it is a power-up reset, a software reset, a user reset, a watchdog reset or a brownout reset. in addition, it controls the internal resets and the nrst pin output. it allows to shape a signal on the nrst line, guaranteeing that the length of the pulse meets any requirement. brownout detector and power-on reset the at91sam7s64 embeds a brownout detection circuit and a power-on reset cell. both are supplied with and monitor vddcore. both signals are provided to the flash to prevent any code corruption during power- up or power-down sequences or if brown- outs occur on the vddcore power supply. the power-on reset cell has a limited-accuracy threshold at around 1.5v. its output remains low during power-up until vddcore goes over this voltage level. this signal goes to the reset controller and allows a full re-initialization of the device. the brownout detector monitors the vddcore level during operation by comparing it to a fixed trigger level. it secures system operations in the most difficult environments and prevents code corruption in case of brownout on the vddcore. only vddcore is monitored, as a vo ltage drop on vddflash or any other power supply of the device cannot affect the flash. when the brownout detector is enabled and vddcore decreases to a value below the trigger level (vbot-, defined as vbot - hyst/2), the brownout output is immediately activated. when vddcore increases above the trigger level (vbot+, defined as vbot + hyst/2), the reset is released. the brownout detector only detects a drop if the voltage on vddcore stays below the threshold voltage for longer than about 1s. the threshold voltage has a hysteresis of about 50 mv, to ensure spike free brownout detection. the typical value of the brownout detector threshold is 1.68v with an accu- racy of 2% and is factory calibrated. the brownout detector is low-power, as it consumes less than 20 a static current. however, it can be deactivated to save its static current. in this case, it consumes less than 1a. the deactivation is configured through the gpnvm bit 0 of the flash.
19 at91sam7s64 preliminary 6070a?atarm?28-oct-04 clock generator the clock generator embeds one low-power rc oscillator, one main oscillator and one pll with the following characteristics: rc oscillator range is between 22 khz and 42 khz main oscillator frequency ranges between 3 and 20 mhz main oscillator can be bypassed pll output ranges between 80 and 200 mhz it provides slck, mainck and pllck. figure 7. clock generator block diagram embedded rc oscillator main oscillator pll and divider clock generator power management controller xin xout pllrc slow clock slck main clock mainck pll clock pllck control status
20 at91sam7s64 preliminary 6070a?atarm?28-oct-04 power management controller the power management controller uses the clock generator outputs to provide: the processor clock pck the master clock mck the usb clock udpck all the peripheral clocks, independently controllable three programmable clock outputs the master clock (mck) is programmable from a few hundred hz to the maximum operating frequency of the device. the processor clock (pck) switches off when entering processor idle mode, thus allow- ing reduced power consumption while waiting for an interrupt. figure 8. power management controller block diagram advanced interrupt controller controls the interrupt lines (nirq and nfiq) of an arm processor individually maskable and vectored interrupt sources ? source 0 is reserved for the fast interrupt input (fiq) ? source 1 is reserved for system peripherals (rtt, pit, efc, pmc, dbgu, etc.) ? other sources control the peripheral interrupts or external interrupts ? programmable edge-triggered or level-sensitive internal sources ? programmable positive/negative edge-triggered or high/low level-sensitive external sources 8-level priority controller ? drives the normal interrupt of the processor ? handles priority of the interrupt sources ? higher priority interrupts can be served during service of lower priority interrupt mck periph_clk[2..14] int udpck usb_suspend slck mainck pllck prescaler /1,/2,/4,...,/64 pck processor clock controller idle mode master clock controller peripherals clock controller on/off usb clock controller on/off slck mainck pllck prescaler /1,/2,/4,...,/64 programmable clock controller pllck divider /1,/2,/4 pck[0..2]
21 at91sam7s64 preliminary 6070a?atarm?28-oct-04 vectoring ? optimizes interrupt service routine branch and execution ? one 32-bit vector register per interrupt source ? interrupt vector register reads the corresponding current interrupt vector protect mode ? easy debugging by preventing automatic operations fast forcing ? permits redirecting any interrupt source on the fast interrupt general interrupt mask ? provides processor synchronization on events without triggering an interrupt debug unit comprises: ? one two-pin uart ? one interface for the debug communication channel (dcc) support ? one set of chip id registers ? one interface providing ice access prevention two-pin uart ? implemented features are compatible with the usart ? programmable baud rate generator ? parity, framing and overrun error ? automatic echo, local loopback and remote loopback channel modes debug communication channel support ? offers visibility of commrx and commtx signals from the arm processor chip id registers ? identification of the device revision, sizes of the embedded memories, set of peripherals ? chip id is 0x27090540 (version 0) periodic interval timer 20-bit programmable counter plus 12-bit interval counter watchdog timer 12-bit key-protected programmable counter running on prescaled slck provides reset or interrupt signals to the system counter may be stopped while the processor is in debug state or in idle mode real-time timer 32-bit free-running counter with alarm running on prescaled slck programmable 16-bit prescaler for slck accuracy compensation pio controller one pio controller, controlling 32 i/o lines fully programmable through set/clear registers multiplexing of two peripheral functions per i/o line for each i/o line (whether assigned to a peripheral or used as general-purpose i/o) ? input change interrupt ? half a clock period glitch filter ? multi-drive option enables driving in open drain
22 at91sam7s64 preliminary 6070a?atarm?28-oct-04 ? programmable pull-up on each i/o line ? pin data status register, supplies visibility of the level on the pin at any time synchronous output, provides set and clear of several i/o lines in a single write voltage regulator controller the aim of this controller is to select the power mode of the voltage regulator between normal mode (bit 0 is cleared) or standby mode (bit 0 is set).
23 at91sam7s64 preliminary 6070a?atarm?28-oct-04 peripherals peripheral mapping each peripheral is allocated 16 kbytes of address space. figure 9. user peripheral mapping peripheral name size 16 kbytes 16 kbytes 0xfffa 0000 0xfffa 3fff tc0, tc1, tc2 timer/counter 0, 1 and 2 16 kbytes 16 kbytes 16 kbytes reserved 0xfffa 4000 0xf000 0000 twi two-wire interface 0xfffb 8000 usart0 universal synchronous asynchronous receiver transmitter 0 0xfffc 0000 0xfffc 3fff usart1 universal synchronous asynchronous receiver transmitter 1 0xfffc 4000 0xfffc 7fff ssc serial synchronous controller 0xfffd 4000 0xfffd 7fff 0xfffd 3fff 0xfffd ffff spi serial peripheral interface 0xfffe 0000 0xfffe 3fff reserved 0xfffe ffff 0xfffe 4000 0xfffb 4000 0xfffb 7fff reserved 0xfff9 ffff 16 kbytes 0xfffc ffff 0xfffd 8000 0xfffd bfff adc analog-to-digital converter 16 kbytes 0xfffc bfff 0xfffc c000 0xfffb ffff reserved 0xfffb c000 0xfffb bfff pwmc 16 kbytes 0xfffa ffff 0xfffb 0000 0xfffb 3fff udp usb device port 16 kbytes reserved reserved 0xfffd 0000 reserved 0xfffd c000 reserved 0xfffc 8000 pwm controller
24 at91sam7s64 preliminary 6070a?atarm?28-oct-04 peripheral multiplexing on pio lines the at91sam7s64 features one pio controller, pioa, that multiplexes the i/o lines of the peripheral set. pio controller a controls 32 lines. each line can be assigned to one of two peripheral functions, a or b. some of them can also be multiplexed with the analog inputs of the adc controller. table 3 on page 25 defines how the i/o lines of the peripherals a, b or the analog inputs are multiplexed on the pio controller a. the two columns ?function? and ?comments? have been inserted for the user?s own comments; they may be used to track how pins are defined in an application. note that some peripheral functions that are output only may be duplicated in the table. all pins reset in their parallel i/o lines function are configured in input with the program- mable pull-up enabled, so that the device is maintained in a static state as soon as a reset is detected.
25 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pio controller a multiplexing table 3. multiplexing on pio controller a pio controller a application usage i/o line peripheral a peripheral b comments function comments pa0 pwm0 tioa0 high-drive pa1 pwm1 tiob0 high-drive pa2 pwm2 sck0 high-drive pa3 twd npcs3 high-drive pa4 tw ck tclk0 pa5 rxd0 npcs3 pa6 txd 0 pck0 pa7 rts0 pwm 3 pa8 cts0 adtrg pa9 drxd npcs1 pa10 dtxd npcs2 pa11 npcs0 pwm0 pa12 miso pwm1 pa13 mosi pwm2 pa14 spc k pwm 3 pa15 tf tioa1 pa16 tk tiob1 pa17 td pck1 ad0 pa18 rd pck2 ad1 pa19 rk fiq ad2 pa20 rf irq0 ad3 pa21 rxd1 pck1 pa22 txd1 npcs3 pa23 sck1 pwm0 pa24 rts1 pwm1 pa25 cts1 pwm2 pa26 dcd1 tioa2 pa27 dtr1 tiob2 pa28 dsr1 tclk1 pa29 ri1 tclk2 pa30 irq1 npcs2 pa31 npcs1 pck2
26 at91sam7s64 preliminary 6070a?atarm?28-oct-04 peripheral identifiers the at91sam7s64 embeds a wide range of peripherals. table 4 defines the peripheral identifiers of the at91sam7s64. a peripheral identifier is required for the control of the peripheral interrupt with the advanced interrupt controller and for the control of the peripheral clock with the power management controller. note: 1. setting sysirq and adc bits in the clock set/clear registers of the pmc has no effect. the system controller is continuously clocked. the adc clock is automati- cally started for the first conversion. in sleep mode the adc clock is automatically stopped after each conversion. serial peripheral interface supports communication with external serial devices ? four chip selects with external decoder allow communication with up to 15 peripherals ? serial memories, such as dataflash ? and 3-wire eeproms ? serial peripherals, such as adcs, dacs, lcd controllers, can controllers and sensors ? external co-processors master or slave serial peripheral bus interface ? 8- to 16-bit programmable data length per chip select ? programmable phase and polarity per chip select ? programmable transfer delays between consecutive transfers and between clock and data per chip select ? programmable delay between consecutive transfers table 4. peripheral identifiers peripheral id peripheral mnemonic peripheral name external interrupt 0 aic advanced interrupt controller fiq 1sysirq (1) system interrupt 2 pioa parallel i/o controller a 3 reserved 4adc (1) analog-to digital converter 5 spi serial peripheral interface 6 us0 usart 0 7 us1 usart 1 8 ssc synchronous serial controller 9 twi two-wire interface 10 pwmc pwm controller 11 udp usb device port 12 tc0 timer/counter 0 13 tc1 timer/counter 1 14 tc2 timer/counter 2 15 - 29 reserved 30 aic advanced interrupt controller irq0 31 aic advanced interrupt controller irq1
27 at91sam7s64 preliminary 6070a?atarm?28-oct-04 ? selectable mode fault detection ? maximum frequency at up to master clock two-wire interface master mode only compatibility with standard two-wire serial memories one, two or three bytes for slave address sequential read/write operations usart programmable baud rate generator 5- to 9-bit full-duplex synchronous or asynchronous serial communications ? 1, 1.5 or 2 stop bits in asynchronous mode ? 1 or 2 stop bits in synchronous mode ? parity generation and error detection ? framing error detection, overrun error detection ? msb or lsb first ? optional break generation and detection ? by 8 or by 16 over-sampling receiver frequency ? hardware handshaking rts - cts ? modem signals management dtr-dsr-dcd-ri on usart1 ? receiver time-out and transmitter timeguard ? multi-drop mode with address generation and detection rs485 with driver control signal iso7816, t = 0 or t = 1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit irda modulation and demodulation ? communication at up to 115.2 kbps test modes ? remote loopback, local loopback, automatic echo serial synchronous controller provides serial synchronous communication links used in audio and telecom applications contains an independent receiver and transmitter and a common clock divider offers a configurable frame sync and data length receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal receiver and transmitter include a data signal, a clock signal and a frame synchronization signal timer counter three 16-bit timer counter channels ? three output compare or two input capture wide range of functions including: ? frequency measurement ? event counting ? interval measurement
28 at91sam7s64 preliminary 6070a?atarm?28-oct-04 ? pulse generation ? delay timing ? pulse width modulation ? up/down capabilities each channel is user-configurable and contains: ? three external clock inputs ? five internal clock inputs, as defined in table 5 ? two multi-purpose input/output signals ? two global registers that act on all three tc channels pwm controller four channels, one 16-bit counter per channel common clock generator, providing thirteen different clocks ? one modulo n counter providing eleven clocks ? two independent linear dividers working on modulo n counter outputs independent channel programming ? independent enable/disable commands ? independent clock selection ? independent period and duty cycle, with double bufferization ? programmable selection of the output waveform polarity ? programmable center or left aligned output waveform usb device port usb v2.0 full-speed compliant,12 mbits per second. embedded usb v2.0 full-speed transceiver embedded 328-byte dual-port ram for endpoints four endpoints ? endpoint 0: 8 bytes ? endpoint 1 and 2: 64 bytes ping-pong ? endpoint 3: 64 bytes ? ping-pong mode (two memory banks) for bulk endpoints suspend/resume logic analog-to-digital converter 8-channel adc 10-bit 100 ksamples/sec. successive approximation register adc -2/+2 lsb integral non linearity, -1/+2 lsb differential non linearity integrated 8-to-1 multiplexer, offering eight independent 3.3v analog inputs table 5. timer counter clocks assignment tc clock input clock timer_clock1 mck/2 timer_clock2 mck/8 timer_clock3 mck/32 timer_clock4 mck/128 timer_clock5 mck/1024
29 at91sam7s64 preliminary 6070a?atarm?28-oct-04 individual enable and disable of each channel external voltage reference for better accuracy on low voltage inputs multiple trigger source ? hardware or software trigger ? external trigger pin ? timer counter 0 to 2 outputs tioa0 to tioa2 trigger sleep mode and conversion sequencer ? automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels four of eight analog inputs shared with digital signals
30 at91sam7s64 preliminary 6070a?atarm?28-oct-04
31 at91sam7s64 preliminary 6070a?atarm?28-oct-04 arm7tdmi processor overview overview the arm7tdmi core executes both the 32-bit arm ? and 16-bit thumb ? instruction sets, allowing the user to trade off between high performance and high code density.the arm7tdmi processor implements von neuman architecture, using a three-stage pipeline consisting of fetch, decode, and execute stages. the main features of the arm7tdmi processor are: arm7tdmi based on armv4t architecture two instruction sets ?arm ? high-performance 32-bit instruction set ? thumb ? high code density 16-bit instruction set three-stage pipeline architecture ? instruction fetch (f) ? instruction decode (d) ? execute (e)
32 at91sam7s64 preliminary 6070a?atarm?28-oct-04 arm7tdmi processor for further details on arm7tdmi, refer to the following arm documents: arm architecture reference manual (ddi 0100e) arm7tdmi technical reference manual (ddi 0210b) instruction type instructions are either 32 bits long (in arm state) or 16 bits long (in thumb state). data type arm7tdmi supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. words must be aligned to four-byte boundaries and half words to two-byte boundaries. unaligned data access behavior depends on which instruction is used where. arm7tdmi operating mode the arm7tdmi, based on arm architecture v4t, supports seven processor modes: user : the normal arm program execution state fiq : designed to support high-speed data transfer or channel process irq : used for general-purpose interrupt handling supervisor : protected mode for the operating system abort mode : implements virtual memory and/or memory protection system : a privileged user mode for the operating system undefined : supports software emulation of hardware coprocessors mode changes may be made under software control, or may be brought about by external interrupts or exception processing. most application programs execute in user mode. the non-user modes, or privileged modes, are entered in order to service interrupts or exceptions, or to access protected resources. arm7tdmi registers the arm7tdmi processor has a total of 37registers: 31 general-purpose 32-bit registers 6 status registers these registers are not accessible at the same time. the processor state and operating mode determine which registers are available to the programmer. at any one time 16 registers are visible to the user. the remainder are synonyms used to speed up exception processing. register 15 is the program counter (pc) and can be used in all instructions to reference data relative to the current instruction. r14 holds the return address after a subroutine call. r13 is used (by software convention) as a stack pointer
33 at91sam7s64 preliminary 6070a?atarm?28-oct-04 . registers r0 to r7 are unbanked registers. this means that each of them refers to the same 32-bit physical register in all processor modes. they are general-purpose registers, with no special uses managed by the architecture, and can be used wherever an instruction allows a general-purpose register to be specified. registers r8 to r14 are banked registers. this means that each of them depends on the cur- rent mode of the processor. modes and exception handling all exceptions have banked registers for r14 and r13. after an exception, r14 holds the return address for exception processing. this address is used to return after the exception is processed, as well as to address the instruction that caused the exception. r13 is banked across exception modes to provide each exception handler with a private stack pointer. the fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without having to save these registers. table 6. arm7tdmi arm modes and registers layout user and system mode supervisor mode abort mode undefined mode interrupt mode fast interrupt mode r0 r0 r0 r0 r0 r0 r1 r1 r1 r1 r1 r1 r2 r2 r2 r2 r2 r2 r3 r3 r3 r3 r3 r3 r4 r4 r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r6 r6 r6 r6 r6 r6 r7 r7 r7 r7 r7 r7 r8 r8 r8 r8 r8 r8_fiq r9 r9 r9 r9 r9 r9_fiq r10 r10 r10 r10 r10 r10_fiq r11 r11 r11 r11 r11 r11_fiq r12 r12 r12 r12 r12 r12_fiq r13 r13_svc r13_abort r13_undef r13_irq r13_fiq r14 r14_svc r14_abort r14_undef r14_irq r14_fiq pc pc pc pc pc pc cpsr cpsr cpsr cpsr cpsr cpsr spsr_svc spsr_abort spsr_undef spsr_irq spsr_fiq mode-specific banked registers
34 at91sam7s64 preliminary 6070a?atarm?28-oct-04 a seventh processing mode, system mode, does not have any banked registers. it uses the user mode registers. system mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions. status registers all other processor states are held in status registers. the current operating processor status is in the current program status register (cpsr). the cpsr holds: four alu flags (negative, zero, carry, and overflow) two interrupt disable bits (one for each type of interrupt) one bit to indicate arm or thumb execution five bits to encode the current processor mode all five exception modes also have a saved program status register (spsr) that holds the cpsr of the task immediately preceding the exception. exception types the arm7tdmi supports five types of exception and a privileged processing mode for each type. the types of exceptions are: fast interrupt (fiq) normal interrupt (irq) memory aborts (used to implement memory protection or virtual memory) attempted execution of an undefined instruction software interrupts (swis) exceptions are generated by internal and external sources. more than one exception can occur in the same time. when an exception occurs, the banked version of r14 and the spsr for the exception mode are used to save state. to return after handling the exception, the spsr is moved to the cpsr, and r14 is moved to the pc. this can be done in two ways: by using a data-processing instruction with the s-bit set, and the pc as the destination by using the load multiple with restore cpsr instruction (ldm) arm instruction set overview the arm instruction set is divided into: branch instructions data processing instructions status register transfer instructions load and store instructions coprocessor instructions exception-generating instructions arm instructions can be executed conditionally. every instruction contains a 4-bit condition code field (bit[31:28]). table 7 gives the arm instruction mnemonic list.
35 at91sam7s64 preliminary 6070a?atarm?28-oct-04 thumb instruction set overview the thumb instruction set is a re-encoded subset of the arm instruction set. the thumb instruction set is divided into: branch instructions data processing instructions load and store instructions load and store multiple instructions exception-generating instruction in thumb mode, eight general-purpose registers, r0 to r7, are available that are the same physical registers as r0 to r7 when executing arm instructions. some thumb instructions also access to the program counter (arm register 15), the link register (arm register 14) table 7. arm instruction mnemonic list mnemonic operation mnemonic operation mov move cdp coprocessor data processing add add mvn move not sub subtract adc add with carry rsb reverse subtract sbc subtract with carry cmp compare rsc reverse subtract with carry tst test cmn compare negated and logical and teq test equivalence eor logical exclusive or bic bit clear mul multiply orr logical (inclusive) or smull sign long multiply mla multiply accumulate smlal signed long multiply accumulate umull unsigned long multiply msr move to status register umlal unsigned long multiply accumulate b branch mrs move from status register bx branch and exchange bl branch and link ldr load word swi software interrupt ldrsh load signed halfword str store word ldrsb load signed byte strh store half word ldrh load half word strb store byte ldrb load byte strbt store register byte with translation ldrbt load register byte with translation strt store register with translation ldrt load register with translation stm store multiple ldm load multiple swpb swap byte swp swap word mrc move from coprocessor mcr move to coprocessor stc store from coprocessor ldc load to coprocessor
36 at91sam7s64 preliminary 6070a?atarm?28-oct-04 and the stack pointer (arm register 13). further instructions allow limited access to the arm registers 8 to 15. table 8 gives the thumb instruction mnemonic list. table 8. thumb instruction mnemonic list mnemonic operation mnemonic operation mov move mvn move not add add adc add with carry sub subtract sbc subtract with carry cmp compare cmn compare negated tst test neg negate and logical and bic bit clear eor logical exclusive or orr logical (inclusive) or lsl logical shift left lsr logical shift right asr arithmetic shift right ror rotate right mul multiply b branch bl branch and link bx branch and exchange swi software interrupt ldr load word str store word ldrh load half word strh store half word ldrb load byte strb store byte ldrsh load signed halfword ldrsb load signed byte ldmia load multiple stmia store multiple push push register to stack pop pop register from stack
37 at91sam7s64 preliminary 6070a?atarm?28-oct-04 at91sam7s64 debug and test features description the at91sam7s64 features a number of complementary debug and test capabilities. a com- mon jtag/ice (in-circuit emulator) port is used for standard debugging functions, such as downloading code and single-stepping through pr ograms. the debug unit provides a two-pin uart that can be used to upload an application into internal sram. it manages the interrupt handling of the internal commtx and commrx signals that trace the activity of the debug communication channel. a set of dedicated debug and test input/output pins gives direct access to these capabilities from a pc-based test environment. block diagram figure 10. debug and test block diagram ice pdc dbgu pio drxd dtxd tst tms tck tdi jtagsel tdo boundary tap ice/jtag tap arm7tdmi reset and test por
38 at91sam7s64 preliminary 6070a?atarm?28-oct-04 application examples debug environment figure 11 on page 38 shows a complete debug environment example. the ice/jtag inter- face is used for standard debugging functions, such as downloading code and single-stepping through the program. figure 11. application debug environment example at91sam7sxx-based application board ice/jtag interface host debugger ice/jtag connector at91sam7sxx terminal rs232 connector
39 at91sam7s64 preliminary 6070a?atarm?28-oct-04 test environment figure 12 on page 39 shows a test environment example. test vectors are sent and inter- preted by the tester. in this example, the ?board in test? is designed using a number of jtag- compliant devices. these devices can be connected to form a single scan chain. figure 12. application test environment example debug and test pin description tester jtag interface ice/jtag connector at91sam7sxx-based application board in test at91sam7sxx test adaptor chip 2 chip n chip 1 table 9. debug and test pin list pin name function type active level reset/test nrst microcontroller reset input/output low tst test mode select input high ice and jtag tck test clock input tdi test data in input tdo test data out output tms test mode select input jtagsel jtag selection input debug unit drxd debug receive data input dtxd debug transmit data output
40 at91sam7s64 preliminary 6070a?atarm?28-oct-04 functional description test pin one dedicated pin, tst, is used to define the device operating mode. the user must make sure that this pin is tied at low level to ensure normal operating conditions. other values asso- ciated with this pin are reserved for manufacturing test. embedded in- circuit emulator the arm7tdmi embedded in-circuit emulator is supported via the ice/jtag port.the inter- nal state of the arm7tdmi is examined through an ice/jtag port. the arm7tdmi processor contains hardware extensions for advanced debugging features: in halt mode, a store-multiple (stm) can be inserted into the instruction pipeline. this exports the contents of the arm7tdmi registers. this data can be serially shifted out without affecting the rest of the system. in monitor mode, the jtag interface is used to transfer data between the debugger and a simple monitor program running on the arm7tdmi processor. there are three scan chains inside the arm7tdmi processor that support testing, debugging, and programming of the embedded ice. the scan chains are controlled by the ice/jtag port. embedded ice mode is selected when jtagsel is low. it is not possible to switch directly between ice and jtag operations. a chip reset must be performed after jtagsel is changed. for further details on the embedded in-circuit-emulator, see the arm7tdmi (rev4) techni- cal reference manual (ddi0210b). debug unit the debug unit provides a two-pin (dxrd and txrd) usart that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum. the debug unit also manages the interrupt handling of the commtx and commrx signals that come from the ice and that trace the activity of the debug communication channel.the debug unit allows blockage of access to the system through the ice interface. the debug unit can be used to upload an application into the internal sram. it is activated by the boot program when no valid application is detected. the protocol used to load the applica- tion is xmodem. a specific register, the debug unit chip id register, gives information about the product ver- sion and its internal configuration. the at91sam7s64 debug unit chip id value is 0x27090540 on 32-bit width. for further details on the debug unit, see?debug unit (dbgu)? on page 179. ieee 1149.1 jtag boundary scan ieee 1149.1 jtag boundary scan allows pin-level access independent of the device packag- ing technology. ieee 1149.1 jtag boundary scan is enabled when jtagsel is high. the sample, extest and bypass functions are implemented. in ice debug mode, the arm processor responds with a non-jtag chip id that identifies the processor to the ice system. this is not ieee 1149.1 jtag-compliant. it is not possible to switch directly between jtag and ice operations. a chip reset must be performed after jtagsel is changed.
41 at91sam7s64 preliminary 6070a?atarm?28-oct-04 a boundary-scan descriptor language (bsdl) file is provided to set up test. jtag boundary-scan register the boundary-scan register (bsr) contains 96 bits that correspond to active pins and associ- ated control signals. each at91sam7s64 input/output pin corresponds to a 3-bit register in the bsr. the out- put bit contains data that can be forced on the pad. the input bit facilitates the observability of data applied to the pad. the control bit selects the direction of the pad. table 10. at91sam7s64 jtag boundary scan register bit number pin name pin type associated bsr cells 96 pa17/pgmd5/ad0 in/out input 95 output 94 control 93 pa18/pgmd6/ad1 in/out input 92 output 91 control 90 pa21/pgmd9 in/out input 89 output 88 control 87 pa19/pgmd7/ad2 in/out input 86 output 85 control 84 pa20/pgmd8/ad3 in/out input 83 output 82 control 81 pa16/pgmd4 in/out input 80 output 79 control 78 pa15/pgm3 in/out input 77 output 76 control 75 pa14/pgmd2 in/out input 74 output 73 control 72 pa13/pgmd1 in/out input 71 output 70 control
42 at91sam7s64 preliminary 6070a?atarm?28-oct-04 69 pa22/pgmd10 in/out input 68 output 67 control 66 pa23/pgmd11 in/out input 65 output 64 control 63 pa24/pgmd12 in/out input 62 output 61 control 60 pa12/pgmd0 in/out input 59 output 58 control 57 pa11/pgmm3 in/out input 56 output 55 control 54 pa10/pgmm2 in/out input 53 output 52 control 51 pa9/pgmm1 in/out input 50 output 49 control 48 pa8/pgmm0 in/out input 47 output 46 control 45 pa7/pgmnvalid in/out input 44 output 43 control 42 pa6/pg mnoe in/out input 41 output 40 control 39 pa5/pgmrdy in/out input 38 output 37 control table 10. at91sam7s64 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
43 at91sam7s64 preliminary 6070a?atarm?28-oct-04 36 pa4/pgmncmd in/out input 35 output 34 control 33 pa25/pgmd13 in/out input 32 output 31 control 30 pa26/pgmd14 in/out input 29 output 28 control 27 pa27/pgmd15 in/out input 26 output 25 control 24 pa28 in/out input 23 output 22 control 21 pa3 in/out input 20 output 19 control 18 pa2 in/out input 17 output 16 control 15 pa1/pgmen1 in/out input 14 output 13 control 12 pa0/pgmen0 in/out input 11 output 10 control 9 pa29 in/out input 8output 7 control 6 pa30 in/out input 5output 4 control table 10. at91sam7s64 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells
44 at91sam7s64 preliminary 6070a?atarm?28-oct-04 id code register access: read-only version[31:28]: product version number set to 0x1. part number[27:12]: product part number set to 0x5b06. manufacturer identity[11:1] set to 0x01f. bit[0] required by ieee std. 1149.1. set to 0x1. jtag id code value is 05b0_603f. 3 pa31 in/out input 2output 1 control 0 erase in input table 10. at91sam7s64 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells 31 30 29 28 27 26 25 24 version part number 23 22 21 20 19 18 17 16 part number 15 14 13 12 11 10 9 8 part number manufacturer identity 76543210 manufacturer identity 1
45 at91sam7s64 preliminary 6070a?atarm?28-oct-04 reset controller (rstc) overview the reset controller (rstc), based on power-on reset cells, handles all the resets of the sys- tem without any external components. it reports which reset occurred last. the reset controller also drives independently or simultaneously the external reset and the peripheral and processor resets. a brownout detection is also available to prevent the processor from falling into an unpredict- able state. block diagram figure 13. reset controller block diagram nrst startup counter proc_nreset wd_fault periph_nreset slck reset state manager reset controller brown_out bod_rst_en rstc_irq nrst manager exter_nreset nrst_out main supply por wdrproc user_reset brownout manager bod_reset
46 at91sam7s64 preliminary 6070a?atarm?28-oct-04 functional description the reset controller is made up of an nrst manager, a brownout manager, a startup counter and a reset state manager. it runs at slow clock and generates the following reset signals: proc_nreset: processor reset line. it also resets the watchdog timer. periph_nreset: affects the whole set of embedded peripherals. nrst_out: drives the nrst pin. these reset signals are asserted by the reset controller, either on external events or on soft- ware action. the reset state manager controls the generation of reset signals and provides a signal to the nrst manager when an assertion of the nrst pin is required. the nrst manager shapes the nrst assertion during a programmable time, thus controlling external device resets. nrst manager the nrst manager samples the nrst input pin and drives this pin low when required by the reset state manager. figure 14 shows the block diagram of the nrst manager. figure 14. nrst manager nrst signal or interrupt the nrst manager samples the nrst pin at slow clock speed. when the line is detected low, a user reset is reported to the reset state manager. however, the nrst manager can be programmed to not trigger a reset when an assertion of nrst occurs. writing the bit ursten at 0 in rstc_mr disables the user reset trigger. the level of the pin nrst can be read at any time in the bit nrstl (nrst level) in rstc_sr. as soon as the pin nrst is asserted, the bit ursts in rstc_sr is set. this bit clears only when rstc_sr is read. the reset controller can also be programmed to generate an interrupt instead of generating a reset. to do so, the bit urstien in rstc_mr must be written at 1. nrst external reset control the reset state manager asserts the signal ext_nreset to assert the nrst pin. when this occurs, the ?nrst_out? signal is driven low by the nrst manager for a time programmed by the field erstl in rstc_mr. this assertion duration, named external_reset_length, lasts 2 (erstl+1) slow clock cycles. this gives the approximate duration of an assertion between 60 s and 2 seconds. note that erstl at 0 defines a two-cycle duration for the nrst pulse. external reset timer ursts ursten erstl exter_nreset urstien rstc_mr rstc_mr rstc_mr rstc_sr nrstl nrst_out nrst rstc_irq other interrupt sources user_reset
47 at91sam7s64 preliminary 6070a?atarm?28-oct-04 this feature allows the reset controller to shape the nrst pin level, and thus to guarantee that the nrst line is driven low for a time compliant with potential external devices connected on the system reset. brownout manager brownout detection prevents the processor from falling into an unpredictable state if the power supply drops below a certain level. when vddcore drops below the brownout threshold, the brownout manager requests a brownout reset by asserting the bod_reset signal. the programmer can disable the brownout reset by setting low the bod_rst_en input signal, i.e.; by locking the corresponding general-purpose nvm bit in the flash. when the brownout reset is disabled, no reset is performed. instead, the brownout detection is reported in the bit bodsts of rstc_sr. bodsts is set and clears only when rstc_sr is read. the bit bodsts can trigger an interrupt if the bit bodien is set in the rstc_mr. at factory, the brownout reset is disabled. figure 15. brownout manager rstc_irq brown_out bod_reset bod_rst_en bodien rstc_mr bodsts rstc_sr other interrupt sources
48 at91sam7s64 preliminary 6070a?atarm?28-oct-04 reset states the reset state manager handles the different reset sources and generates the internal reset signals. it reports the reset status in the field rsttyp of the status register (rstc_sr). the update of the field rsttyp is performed when the processor reset is released. power-up reset when vddcore is powered on, the main supply por cell output is filtered with a start-up counter that operates at slow clock. the purpose of this counter is to ensure that the slow clock oscillator is stable before starting up the device. the startup time, as shown in figure 16, is hardcoded to comply with the slow clock oscillator startup time. after the startup time, the reset signals are released and the field rsttyp in rstc_sr reports a power-up reset. when vddcore is detected low by the main supply por cell, all reset signals are asserted immediately. figure 16. power-up reset slck periph_nreset proc_nreset main supply por output nrst (nrst_out) external reset length = 2 cycles startup time mck processor startup = 3 cycles any freq.
49 at91sam7s64 preliminary 6070a?atarm?28-oct-04 user reset the user reset is entered when a low level is detected on the nrst pin and the bit ursten in rstc_mr is at 1. the nrst input signal is resynchronized with slck to insure proper behavior of the system. the user reset is entered as soon as a low level is detected on nrst. the processor reset and the peripheral reset are asserted. the user reset is left when nrst rises, after a two-cycle resynchronization time and a three- cycle processor startup. the processor clock is re-enabled as soon as nrst is confirmed high. when the processor reset signal is released, the rsttyp field of the status register (rstc_sr) is loaded with the value 0x4, indicating a user reset. the nrst manager guarantees that the nrst line is asserted for external_reset_length slow clock cycles, as programmed in the field erstl. how- ever, if nrst does not rise after external_r eset_length because it is driven low externally, the internal reset lines remain asserted until nrst actually rises. figure 17. user reset state slck periph_nreset proc_nreset nrst nrst (nrst_out) >= external reset length mck processor startup = 3 cycles any freq. resynch. 2 cycles rsttyp any xxx resynch. 2 cycles 0x4 = user reset
50 at91sam7s64 preliminary 6070a?atarm?28-oct-04 brownout reset when the brown_out/bod_reset signal is asserted, the reset state manager immediately enters the brownout reset. in this state, the processor, the peripheral and the external reset lines are asserted. the brownout reset is left 3 slow clock cycles after the rising edge of brown_out/bod_reset after a two-cycle resynchronization. an external reset is also triggered. when the processor reset is released, the field rsttyp in rstc_sr is loaded with the value 0x5, thus indicating that the last reset is a brownout reset. figure 18. brownout reset state slck periph_nreset proc_nreset brown_out or bod_reset nrst (nrst_out) external reset length 8 cycles (erstl=2) mck processor startup = 3 cycles any freq. rsttyp any xxx 0x5 = brownout reset resynch. 2 cycles
51 at91sam7s64 preliminary 6070a?atarm?28-oct-04 software reset the reset controller offers several commands used to assert the different reset signals. these commands are performed by writing the control register (rstc_cr) with the following bits at 1: procrst: writing procrst at 1 resets the processor and the watchdog timer. perrst: writing perrst at 1 resets all the embedded peripherals, including the memory system, and, in particular, the remap command. the peripheral reset is generally used for debug purposes. extrst: writing extrst at 1 asserts low the nrst pin during a time defined by the field erstl in the mode register (rstc_mr). the software reset is entered if at least one of these bits is set by the software. all these com- mands can be performed independently or simultaneously. the software reset lasts 3 slow clock cycles. the internal reset signals are asserted as soon as the register write is performed. this is detected on the master clock (mck). they are released when the software reset is left, i.e.; synchronously to slck. if extrst is set, the nrst_out signal is asserted depending on the programming of the field erstl. however, the resulting falling edge on nrst does not lead to a user reset. if and only if the procrst bit is set, the reset controller reports the software status in the field rsttyp of the status register (rstc_sr). other software resets are not reported in rsttyp. as soon as a software operation is detected, the bit srcmp (software reset command in progress) is set in the status register (rstc_sr). it is cleared as soon as the software reset is left. no other software reset can be performed while the srcmp bit is set, and writing any value in rstc_cr has no effect. figure 19. software reset slck periph_nreset if perrst=1 proc_nreset if procrst=1 write rstc_cr nrst (nrst_out) if extrst=1 external reset length 8 cycles (erstl=2) mck processor startup = 3 cycles any freq. rsttyp any xxx 0x3 = software reset resynch. 1 cycle srcmp in rstc_sr
52 at91sam7s64 preliminary 6070a?atarm?28-oct-04 watchdog reset the watchdog reset is entered when a watchdog fault occurs. this state lasts 3 slow clock cycles. when in watchdog reset, assertion of the reset signals depends on the wdrproc bit in wdt_mr: if wdrproc is 0, the processor reset and the peripheral reset are asserted. the nrst line is also asserted, depending on the programming of the field erstl. however, the resulting low level on nrst does not result in a user reset state. if wdrproc = 1, only the processor reset is asserted. the watchdog timer is reset by the proc_nreset signal. as the watchdog fault always causes a processor reset if wdrsten is set, the watchdog timer is always reset after a watchdog reset, and the watchdog is enabled by default and with a period set to a maximum. when the wdrsten in wdt_mr bit is reset, the watchdog fault has no impact on the reset controller. figure 20. watchdog reset only if wdrproc = 0 slck periph_nreset proc_nreset wd_fault nrst (nrst_out) external reset length 8 cycles (erstl=2) mck processor startup = 3 cycles any freq. rsttyp any xxx 0x2 = watchdog reset
53 at91sam7s64 preliminary 6070a?atarm?28-oct-04 reset state priorities the reset state manager manages the following priorities between the different reset sources, given in descending order: power-up reset brownout reset watchdog reset software reset user reset particular cases are listed below: when in user reset: ? a watchdog event is impossible because the watchdog timer is being reset by the proc_nreset signal. ? a software reset is impossible, since the processor reset is being activated. when in software reset: ? a watchdog event has priority over the current state. ? the nrst has no effect. when in watchdog reset: ? the processor reset is active and so a software reset cannot be programmed. ? a user reset cannot be entered. reset controller status register the reset controller status register (rstc_sr) provides several status fields: rsttyp field: this field gives the type of the last reset, as explained in previous sections. srcmp bit: this field indicates that a software reset command is in progress and that no further software reset should be performed until the end of the current one. this bit is automatically cleared at the end of the current software reset. nrstl bit: the nrstl bit of the status register gives the level of the nrst pin sampled on each mck rising edge. ursts bit: a high-to-low transition of the nrst pin sets the ursts bit of the rstc_sr register. this transition is also detected on the master clock (mck) rising edge (see figure 21). if the user reset is disabled (ursten = 0) and if the interruption is enabled by the urstien bit in the rstc_mr register, the ursts bit triggers an interrupt. reading the rstc_sr status register resets the ursts bit and clears the interrupt. bodsts bit: this bit indicates a brownout detection when the brownout reset is disabled (bod_rst_en = 0). it triggers an interrupt if the bit bodien in the rstc_mr register enables the interrupt. reading the rstc_sr register resets the bodsts bit and clears the interrupt.
54 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 21. reset controller status and interrupt mck nrst nrstl 2 cycle resynchronization 2 cycle resynchronization ursts read rstc_sr peripheral access rstc_irq if (ursten = 0) and (urstien = 1)
55 at91sam7s64 preliminary 6070a?atarm?28-oct-04 reset controller (rstc) user interface table 11. reset controll er registers offset register name access reset value 0x00 control register rstc_cr write-only - 0x04 status register rstc_sr read-only 0x0000_0000 0x08 mode register rstc_mr read/write 0x0000_0000
56 at91sam7s64 preliminary 6070a?atarm?28-oct-04 reset controller control register register name: rstc_cr access type: write-only procrst: processor reset 0 = no effect. 1 = if key is correct, resets the processor. perrst: peripheral reset 0 = no effect. 1 = if key is correct, resets the peripherals. extrst: external reset 0 = no effect. 1 = if key is correct, asserts the nrst pin. key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ? 76543210 ????extrstperrst?procrst
57 at91sam7s64 preliminary 6070a?atarm?28-oct-04 reset controller status register register name: rstc_sr access type: read-only ursts: user reset status 0 = no high-to-low edge on nrst happened since the last read of rstc_sr. 1 = at least one high-to-low transition of nrst has been detected since the last read of rstc_sr. bodsts: brownout detection status 0 = no brownout high-to-low transition happened since the last read of rstc_sr. 1 = a brownout high-to-low transition has been detected since the last read of rstc_sr. rsttyp: reset type reports the cause of the last processor reset. reading this rstc_sr does not reset this field. nrstl: nrst pin level registers the nrst pin level at master clock (mck). srcmp: software reset command in progress 0 = no software command is being performed by the reset controller. the reset controller is ready for a software command. 1 = a software reset command is being performed by the reset controller. the reset controller is busy. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ??????srcmpnrstl 15 14 13 12 11 10 9 8 ????? rsttyp 76543210 ??????bodstsursts rsttyp reset type comments 0 0 0 power-up reset vddcore rising 0 1 0 watchdog reset watchdog fault occurred 0 1 1 software reset processor reset required by the software 1 0 0 user reset nrst pin detected low 1 0 1 brownout reset brownout reset occurred
58 at91sam7s64 preliminary 6070a?atarm?28-oct-04 reset controller mode register register name: rstc_mr access type: read/write ursten: user reset enable 0 = the detection of a low level on the pin nrst does not generate a user reset. 1 = the detection of a low level on the pin nrst triggers a user reset. urstien: user reset interrupt enable 0 = usrts bit in rstc_sr at 1 has no effect on rstc_irq. 1 = usrts bit in rstc_sr at 1 asserts rstc_irq if ursten = 0. bodien: brownout detection interrupt enable 0 = bodsts bit in rstc_sr at 1 has no effect on rstc_irq. 1 = bodsts bit in rstc_sr at 1 asserts rstc_irq. erstl: external reset length this field defines the external reset length. the external reset is asserted during a time of 2 (erstl+1) slow clock cycles. this allows assertion duration to be programmed between 60 s and 2 seconds. key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????bodien 15 14 13 12 11 10 9 8 ???? erstl 76543210 ? ? urstien ? ? ? ursten
59 at91sam7s64 preliminary 6070a?atarm?28-oct-04 real-time timer (rtt) overview the real-time timer is built around a 32-bit counter and used to count elapsed seconds. it generates a periodic interrupt or/and triggers an alarm on a programmed value. block diagram figure 22. real-time timer slck rtpres rttinc alms 16-bit divider 32-bit counter almv = crtv rtt_mr rtt_vr rtt_ar rtt_sr rttincien rtt_mr 0 10 almien rtt_int rtt_mr set set rtt_sr read rtt_sr reset reset rtt_mr reload rtt_alarm rttrst rtt_mr rttrst
60 at91sam7s64 preliminary 6070a?atarm?28-oct-04 functional description the real-time timer is used to count elapsed seconds. it is built around a 32-bit counter fed by slow clock divided by a programmable 16-bit value. the value can be programmed in the field rtpres of the real-time mode register (rtt_mr). programming rtpres at 0x00008000 corresponds to feeding the real-time counter with a 1 hz signal (if the slow clock is 32.768 hz). the 32-bit counter can count up to 2 32 seconds, corresponding to more than 136 years, then roll over to 0. the real-time timer can also be used as a free-running timer with a lower time-base. the best accuracy is reached by writing rtpres at 1. in this case, the period of the signal pro- vided to the real-time timer counter is 30.52 s (when slow clock is 32.768 hz) and the maximum the real-time timer can cover is 131072 seconds, corresponding to more than 36 days. the real-time timer value (crtv) can be read at any time in the register rtt_vr (real-time value register). as this value can be updated asynchronously from the master clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value. the current value of the counter is compared with the value written in the alarm register rtt_ar (real-time alarm register). if the counter value matches the alarm, the bit alms in rtt_sr is set. the alarm register is set to its maximum value, corresponding to 0xffff_ffff, after a reset. the bit rttinc in rtt_sr is set each time the real-time timer counter is incremented. this bit can be used to start a periodic interrupt, the period being one second when the rtpres is programmed with 0x8000 and slow clock equal to 32.768 hz. reading the rtt_sr status register resets the rttinc and alms fields. writing the bit rttrst in rtt_mr immediately reloads and restarts the clock divider with the new programmed value. this also resets the 32-bit counter.
61 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 23. rtt counting prescaler almv almv-1 0 almv+1 0 rtpres - 1 rtt apb cycle read rtt_sr alms (rtt_sr) apb interface mck rttinc (rtt_sr) almv+2 almv+3 ... apb cycle
62 at91sam7s64 preliminary 6070a?atarm?28-oct-04 real-time timer (rtt) user interface table 12. real-time timer register mapping offset register name access reset value 0x00 mode register rtt_mr read/write 0x0000_8000 0x04 alarm register rtt_ar read/write 0xffff_ffff 0x08 value register rtt_vr read-only 0x0000_0000 0x0c status register rtt_sr read-only 0x0000_0000
63 at91sam7s64 preliminary 6070a?atarm?28-oct-04 real-time timer mode register register name: rtt_mr access type: read/write rtpres: real-time timer prescaler value defines the number of slck periods required to increment the real-time timer. rtpres is defined as follows: rtpres = 0: the prescaler period is equal to 2 16 rtpres 0: the prescaler period is equal to rtpres. almien: alarm interrupt enable 0 = the bit alms in rtt_sr has no effect on interrupt. 1 = the bit alms in rtt_sr asserts interrupt. rttincien: real-time timer increment interrupt enable 0 = the bit rttinc in rtt_sr has no effect on interrupt. 1 = the bit rttinc in rtt_sr asserts interrupt. rttrst: real-time timer restart 1 = reloads and restarts the clock divider with the new programmed value. this also resets the 32-bit counter. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?????rttrstrttincienalmien 15 14 13 12 11 10 9 8 rtpres 76543210 rtpres
64 at91sam7s64 preliminary 6070a?atarm?28-oct-04 real-time timer alarm register register name: rtt_ar access type: read/write almv: alarm value defines the alarm value (almv+1) compared with the real-time timer. 31 30 29 28 27 26 25 24 almv 23 22 21 20 19 18 17 16 almv 15 14 13 12 11 10 9 8 almv 76543210 almv
65 at91sam7s64 preliminary 6070a?atarm?28-oct-04 real-time timer value register register name: rtt_vr access type: read-only crtv: current real-time value returns the current value of the real-time timer. 31 30 29 28 27 26 25 24 crtv 23 22 21 20 19 18 17 16 crtv 15 14 13 12 11 10 9 8 crtv 76543210 crtv
66 at91sam7s64 preliminary 6070a?atarm?28-oct-04 real-time timer status register register name: rtt_sr access type: read-only alms: real-time alarm status 0 = the real-time alarm has not occurred since the last read of rtt_sr. 1 = the real-time alarm occurred since the last read of rtt_sr. rttinc: real-time timer increment 0 = the real-time timer has not been incremented since the last read of the rtt_sr. 1 = the real-time timer has been incremented since the last read of the rtt_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????rttincalms
67 at91sam7s64 preliminary 6070a?atarm?28-oct-04 periodic interval timer (pit) overview the periodic interval timer (pit) provides the operating system?s scheduler interrupt. it is designed to offer maximum accuracy and efficient management, even for systems with long response time. block diagram figure 24. periodic interval timer 20-bit counter mck/16 piv pit_mr cpiv pit_pivr picnt 12-bit adder 0 0 read pit_pivr cpiv picnt pit_piir pits pit_sr set reset pitien pit_mr pit_irq 1 0 1 0 mck prescaler = ?
68 at91sam7s64 preliminary 6070a?atarm?28-oct-04 functional description the periodic interval timer aims at providing periodic interrupts for use by operating systems. the pit provides a programmable overflow counter and a reset-on-read feature. it is built around two counters: a 20-bit cpiv counter and a 12-bit picnt counter. both counters work at master clock /16. the first 20-bit cpiv counter increments from 0 up to a programmable overflow value set in the field piv of the mode register (pit_mr). when the counter cpiv reaches this value, it resets to 0 and increments the periodic interval counter, picnt. the status bit pits in the status register (pit_sr) rises and triggers an interrupt, provided the interrupt is enabled (pitien in pit_mr). writing a new piv value in pit_mr does not reset/restart the counters. when cpiv and picnt values are obtained by reading the periodic interval value register (pit_pivr), the overflow counter (picnt) is reset and the pits is cleared, thus acknowledg- ing the interrupt. the value of picnt gives the number of periodic intervals elapsed since the last read of pit_pivr. when cpiv and picnt values are obtained by reading the periodic interval image register (pit_piir), there is no effect on the counters cpiv and picnt, nor on the bit pits. for exam- ple, a profiler can read pit_piir without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading pit_pivr. the pit may be enabled/disabled using the piten bit in the pit_mr register (disabled on reset). the piten bit only becomes effective when the cpiv value is 0. figure 25 illustrates the pit counting. after the pit enable bit is reset (piten= 0), the cpiv goes on counting until the piv value is reached, and is then reset. pit restarts counting, only if the piten is set again. the pit is stopped when the core enters debug state.
69 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 25. enabling/disabling pit with piten mck prescaler piv piv - 1 0 piten 10 0 15 cpiv 1 restarts mck prescaler 0 1 apb cycle read pit_pivr 0 picnt pits (pit_sr) mck apb interface apb cycle
70 at91sam7s64 preliminary 6070a?atarm?28-oct-04 periodic interval timer (pit) user interface table 13. periodic interval timer (pit) register mapping offset register name access reset value 0x00 mode register pit_mr read/write 0x000f_ffff 0x04 status register pit_sr read-only 0x0000_0000 0x08 periodic interval value register pit_pivr read-only 0x0000_0000 0x0c periodic interval image register pit_piir read-only 0x0000_0000
71 at91sam7s64 preliminary 6070a?atarm?28-oct-04 periodic interval timer mode register register name: pit_mr access type: read/write piv: periodic interval value defines the value compared with the primary 20-bit counter of the periodic interval timer (cpiv). the period is equal to (piv + 1). piten: period interval timer enabled 0 = the periodic interval timer is disabled when the piv value is reached. 1 = the periodic interval timer is enabled. pitien: periodic interval timer interrupt enable 0 = the bit pits in pit_sr has no effect on interrupt. 1 = the bit pits in pit_sr asserts interrupt. 31 30 29 28 27 26 25 24 ??????pitienpiten 23 22 21 20 19 18 17 16 ???? piv 15 14 13 12 11 10 9 8 piv 76543210 piv
72 at91sam7s64 preliminary 6070a?atarm?28-oct-04 periodic interval timer status register register name: pit_sr access type: read-only pits: periodic interval timer status 0 = the periodic interval timer has not reached piv since the last read of pit_pivr. 1 = the periodic interval timer has reached piv since the last read of pit_pivr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????pits
73 at91sam7s64 preliminary 6070a?atarm?28-oct-04 periodic interval timer value register register name: pit_pivr access type: read-only reading this register clears pits in pit_sr. cpiv: current periodic interval value returns the current value of the periodic interval timer. picnt: periodic interval counter returns the number of occurrences of periodic intervals since the last read of pit_pivr. 31 30 29 28 27 26 25 24 picnt 23 22 21 20 19 18 17 16 picnt cpiv 15 14 13 12 11 10 9 8 cpiv 76543210 cpiv
74 at91sam7s64 preliminary 6070a?atarm?28-oct-04 periodic interval timer image register register name: pit_piir access type: read-only cpiv: current periodic interval value returns the current value of the periodic interval timer. picnt: periodic interval counter returns the number of occurrences of periodic intervals since the last read of pit_pivr. 31 30 29 28 27 26 25 24 picnt 23 22 21 20 19 18 17 16 picnt cpiv 15 14 13 12 11 10 9 8 cpiv 76543210 cpiv
75 at91sam7s64 preliminary 6070a?atarm?28-oct-04 watchdog timer (wdt) overview the watchdog timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. it features a 12-bit down counter that allows a watchdog period of up to 16 sec- onds (slow clock at 32.768 khz). it can generate a general reset or a processor reset only. in addition, it can be stopped while the processor is in debug mode or idle mode. block diagram figure 26. watchdog timer block diagram = 0 10 set reset read wdt_sr or reset wdt_fault (to reset controlle r) set reset wdfien wdt_int wdt_mr slck 1/128 12-bit down counter current value wdd wdt_mr <= wdd wv wdrstt wdt_mr wdt_cr reload wdunf wderr reload write wdt_mr wdrsten wdt_mr
76 at91sam7s64 preliminary 6070a?atarm?28-oct-04 functional description the watchdog timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. it is supplied with vddcore. it restarts with initial values on processor reset. the watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field wv of the mode register (wdt_mr). the watchdog timer uses the slow clock divided by 128 to establish the maximum watchdog period to be 16 seconds (with a typical slow clock of 32.768 khz). after a processor reset, the value of wv is 0xfff, corresponding to the maximum value of the counter with the external reset generation enabled (field wdrsten at 1 after a backup reset). this means that a default watchdog is running at reset, i.e., at power-up. the user must either disable it (by setting the wddis bit in wdt_mr) if he does not expect to use it or must reprogram it to meet the maximum watchdog period the application requires. the watchdog mode register (wdt_mr) can be written only once. only a processor reset resets it. writing the wdt_mr register reloads the timer with the newly programmed mode parameters. in normal operation, the user reloads the watchdog at regular intervals before the timer under- flow occurs, by writing the control register (wdt_cr) with the bit wdrstt to 1. the watchdog counter is then immediately reloaded from wdt_mr and restarted, and the slow clock 128 divider is reset and restarted. the wdt_cr register is write-protected. as a result, writing wdt_cr without the correct hard-coded key has no effect. if an underflow does occur, the ?wdt_fault? signal to the reset controller is asserted if the bit wdrsten is set in the mode register (wdt_mr). moreover, the bit wdunf is set in the watchdog status register (wdt_sr). to prevent a software deadlock that continuously triggers the watchdog, the reload of the watchdog must occur in a window defined by 0 and wdd in the wdt_mr: 0 wdt wdd; writing wdrstt restarts the watchdog timer. any attempt to restart the watchdog timer in the range [wdv; wdd] results in a watchdog error, even if the watchdog is disabled. the bit wderr is updated in the wdt_sr and the ?wdt_fault? signal to the reset controller is asserted. note that this feature can be disabled by programming a wdd value greater than or equal to the wdv value. in such a configuration, restarting the watchdog timer is permitted in the whole range [0; wdv] and does not generate an error. this is the default configuration on reset (the wdd and wdv values are equal). the status bits wdunf (watchdog underflow) and wderr (watchdog error) trigger an inter- rupt, provided the bit wdfien is set in the mode register. the signal ?wdt_fault? to the reset controller causes a watchdog reset if the wdrsten bit is set as already explained in the reset controller programmer datasheet. in that case, the processor and the watchdog timer are reset, and the wderr and wdunf flags are reset. if a reset is generated or if wdt_sr is read, the status bits are reset, the interrupt is cleared, and the ?wdt_fault? signal to the reset controller is deasserted. writing the wdt_mr reloads and restarts the down counter. while the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits wdidlehlt and wddbghlt in the wdt_mr.
77 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 27. watchdog behavior 0 wdv wdd wdt_cr = wdrstt watchdog fault normal behavior watchdog error watchdog underflow fff if wdrsten is 1 if wdrsten is 0 forbidden window permitted window
78 at91sam7s64 preliminary 6070a?atarm?28-oct-04 watchdog timer (wdt) user interface table 14. watchdog timer (wdt) register mapping offset register name access reset value 0x00 control register wdt_cr write-only - 0x04 mode register wdt_mr read/write once 0x3fff_2fff 0x08 status register wdt_sr read-only 0x0000_0000
79 at91sam7s64 preliminary 6070a?atarm?28-oct-04 watchdog timer control register register name: wdt_cr access type: write-only wdrstt: watchdog restart 0: no effect. 1: restarts the watchdog. key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????wdrstt
80 at91sam7s64 preliminary 6070a?atarm?28-oct-04 watchdog timer mode register register name: wdt_mr access type: read / write once wdv: watchdog counter value defines the value loaded in the 12-bit watchdog counter. wdfien: watchdog fault interrupt enable 0: a watchdog fault (underflow or error) has no effect on interrupt. 1: a watchdog fault (underflow or error) asserts interrupt. wdrsten: watchdog reset enable 0: a watchdog fault (underflow or error) has no effect on the resets. 1: a watchdog fault (underflow or error) triggers a watchdog reset. wdrproc: watchdog reset processor 0: if wdrsten is 1, a watchdog fault (underflow or error) activates all resets. 1: if wdrsten is 1, a watchdog fault (underflow or error) activates the processor reset. wdd: watchdog delta value defines the permitted range for reloading the watchdog timer. if the watchdog timer value is less than or equal to wdd, writing wdt_cr with wdrstt = 1 restarts the timer. if the watchdog timer value is greater than wdd, writing wdt_cr with wdrstt = 1 causes a watchdog error. wddbghlt: watchdog debug halt 0: the watchdog runs when the processor is in debug state. 1: the watchdog stops when the processor is in debug state. wdidlehlt: watchdog idle halt 0: the watchdog runs when the system is in idle mode. 1: the watchdog stops when the system is in idle state. wddis: watchdog disable 0: enables the watchdog timer. 1: disables the watchdog timer. 31 30 29 28 27 26 25 24 wdidlehlt wddbghlt wdd 23 22 21 20 19 18 17 16 wdd 15 14 13 12 11 10 9 8 wddis wdrproc wdrsten wdfien wdv 76543210 wdv
81 at91sam7s64 preliminary 6070a?atarm?28-oct-04 watchdog timer status register register name: wdt_sr access type: read-only wdunf: watchdog underflow 0: no watchdog underflow occurred since the last read of wdt_sr. 1: at least one watchdog underflow occurred since the last read of wdt_sr. wderr: watchdog error 0: no watchdog error occurred since the last read of wdt_sr. 1: at least one watchdog error occurred since the last read of wdt_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????wderrw dunf
82 at91sam7s64 preliminary 6070a?atarm?28-oct-04
83 at91sam7s64 preliminary 6070a?atarm?28-oct-04 voltage regulator mode controller (vreg) overview the voltage regulator mode controller contains one read/write register, the voltage regula- tor mode register. its offset is 0x60 with respect to the system controller offset. this register controls the voltage regulator mode. setting pstdby (bit 0) puts the voltage regulator in standby mode or low-power mode. on reset, the pstdby is reset, so as to wake up the voltage regulator in normal mode. voltage regulator power controller (vreg) user interface voltage regulator mode register register name: vreg_mr access type: read/write pstdby: periodic interval value 0 = voltage regulator in normal mode. 1 = voltage regulator in standby mode (low-power mode). table 15. voltage regulator power controller register mapping offset register name access reset value 0x60 voltage regulator mode register vreg_mr read/write 0x0 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????pstdby
84 at91sam7s64 preliminary 6070a?atarm?28-oct-04
85 at91sam7s64 preliminary 6070a?atarm?28-oct-04 memory controller (mc) overview the memory controller (mc) manages the asb bus and controls accesses requested by the masters, typically the arm7tdmi processor and the peripheral data controller. it features a simple bus arbiter, an address decoder, an abort status, a misalignment detector and an embedded flash controller. block diagram figure 28. memory controller block diagram arm7tdmi processor bus arbiter peripheral data controller memory controller abort asb abort status address decoder user interface peripheral 0 peripheral 1 internal ram apb apb bridge misalignment detector from master to slave peripheral n embedded flash controller internal flash
86 at91sam7s64 preliminary 6070a?atarm?28-oct-04 functional description the memory controller handles the internal asb bus and arbitrates the accesses of both masters. it is made up of: a bus arbiter an address decoder an abort status a misalignment detector an embedded flash controller the mc handles only little-endian mode accesses. the masters work in little-endian mode only. bus arbiter the memory controller has a simple, hard-wired priority bus arbiter that gives the control of the bus to one of the two masters. the peripheral data controller has the highest priority; the arm processor has the lowest one. address decoder the memory controller features an address decoder that first decodes the four highest bits of the 32-bit address bus and defines three separate areas: one 256-mbyte address space for the internal memories one 256-mbyte address space reserved for the embedded peripherals an undefined address space of 3584m bytes representing fourteen 256-mbyte areas that return an abort if accessed figure 29 shows the assignment of the 256-mbyte memory areas. figure 29. memory areas 0x0000 0000 0x0fff ffff 0x1000 0000 0xefff ffff 0xf000 0000 0xffff ffff 256m bytes 256m bytes 14 x 256mbytes 3,584 mbytes internal memories undefined (abort) peripherals
87 at91sam7s64 preliminary 6070a?atarm?28-oct-04 internal memory mapping within the internal memory address space, the address decoder of the memory controller decodes eight more address bits to allocate 1-mbyte address spaces for the embedded memories. the allocated memories are accessed all along the 1-mbyte address space and so are repeated n times within this address space, n equaling 1m bytes divided by the size of the memory. when the address of the access is undefined within the internal memory area, the address decoder returns an abort to the master. figure 30. internal memory mapping internal memory area 0 the first 32 bytes of internal memory area 0 contain the arm processor exception vectors, in particular, the reset vector at address 0x0. before execution of the remap command, the on-chip flash is mapped into internal memory area 0, so that the arm7tdmi reaches an executable instruction contained in flash. after the remap command, the internal sram at address 0x0020 0000 is mapped into internal memory area 0. the memory mapped into internal memory area 0 is accessible in both its original location and at address 0x0. remap command after execution, the remap command causes the internal sram to be accessed through the internal memory area 0. as the arm vectors (reset, abort, data abort, prefetch abort, undefined instruction, inter- rupt, and fast interrupt) are mapped from address 0x0 to address 0x20, the remap command allows the user to redefine dynamically these vectors under software control. the remap command is accessible through the memory controller user interface by writing the mc_rcr (remap control register) rcb field to one. the remap command can be cancelled by writing the mc_rcr rcb field to one, which acts as a toggling command. this allows easy debug of the user-defined boot sequence by offering a simple way to put the chip in the same configuration as after a reset. 256m bytes internal memory area 0 undefined areas (abort) 0x0000 0000 0x000f ffff 0x0010 0000 0x001f ffff 0x0020 0000 0x002f ffff 0x0fff ffff 1m bytes 1m bytes 1m bytes 253m bytes internal memory area 1 internal flash internal memory area 2 internal sram 0x0030 0000
88 at91sam7s64 preliminary 6070a?atarm?28-oct-04 abort status there are three reasons for an abort to occur: access to an undefined address an access to a misaligned address. when an abort occurs, a signal is sent back to all the masters, regardless of which one has generated the access. however, only the arm7tdmi can take an abort signal into account, and only under the condition that it was generating an access. the peripheral data controller does not handle the abort input signal. note that the connection is not represented in figure 28. to facilitate debug or for fault analysis by an operating system, the memory controller inte- grates an abort status register set. the full 32-bit wide abort address is saved in mc_ aasr. parameters of the access are saved in mc_asr and include: the size of the request (field abtsz) the type of the access, whether it is a data read or write, or a code fetch (field abttyp) whether the access is due to accessing an undefined address (bit undadd) or a misaligned address (bit misadd) the source of the access leading to the last abort (bits mst0 and mst1) whether or not an abort occurred for each master since the last read of the register (bit svmst0 and svmst1) unless this information is loaded in mst bits in the case of a data abort from the processor, the address of the data access is stored. this is useful, as searching for which address generated the abort would require disassembling the instructions and full knowledge of the processor context. in the case of a prefetch abort, the address may have changed, as the prefetch abort is pipe- lined in the arm processor. the arm processor takes the prefetch abort into account only if the read instruction is executed and it is probable that several aborts have occurred during this time. thus, in this case, it is preferable to use the content of the abort link register of the arm processor. embedded flash controller the embedded flash controller is added to the memory controller and ensures the interface of the flash block with the 32-bit internal bus. it increases performance in thumb mode for code fetch with its system of 32-bit buffers. it also manages with the programming, erasing, locking and unlocking sequences thanks to a full set of commands. misalignment detector the memory controller features a misalignment detector that checks the consistency of the accesses. for each access, regardless of the master, the size of the access and the bits 0 and 1 of the address bus are checked. if the type of access is a word (32-bit) and the bits 0 and 1 are not 0, or if the type of the access is a half-word (16-bit) and the bit 0 is not 0, an abort is returned to the master and the access is cancelled. note that the accesses of the arm processor when it is fetching instructions are not checked. the misalignments are generally due to software bugs leading to wrong pointer handling. these bugs are particularly difficult to detect in the debug phase. as the requested address is saved in the abort status register and the address of the instruc- tion generating the misalignment is saved in the abort link register of the processor, detection and fix of this kind of software bug is simplified.
89 at91sam7s64 preliminary 6070a?atarm?28-oct-04 memory controller (mc) user interface base address : 0xffffff00 table 16. memory controller (mc) register mapping offset register name access reset state 0x00 mc remap control register mc_rcr write-only 0x04 mc abort status register mc_asr read-only 0x0 0x08 mc abort address status register mc_aasr read-only 0x0 0x0c-0x5c reserved ? ? ? 0x60 efc configuration registers see ?embedded flash controller (efc)? on page 93.
90 at91sam7s64 preliminary 6070a?atarm?28-oct-04 mc remap control register register name : mc_rcr access type : write-only offset :0x00 rcb: remap command bit 0: no effect. 1: this command bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of the page zero memory devices. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????rcb
91 at91sam7s64 preliminary 6070a?atarm?28-oct-04 mc abort status register register name : mc_asr access type : read-only reset value :0x0 offset :0x04 undadd: undefined address abort status 0: the last abort was not due to the access of an undefined address in the address space. 1: the last abort was due to the access of an undefined address in the address space. misadd: misaligned address abort status 0: the last aborted access was not due to an address misalignment. 1: the last aborted access was due to an address misalignment. abtsz: abort size status. abttyp: abort type status. mst0: arm7tdmi abort source 0: the last aborted access was not due to the arm7tdmi. 1: the last aborted access was due to the arm7tdmi. mst1: pdc abort source 0: the last aborted access was not due to the pdc. 1: the last aborted access was due to the pdc. 31 30 29 28 27 26 25 24 ??????svmst1svmst0 23 22 21 20 19 18 17 16 ??????mst1mst0 15 14 13 12 11 10 9 8 ? ? ? ? abttyp abtsz 76543210 ??????misadd undadd abtsz abort size 0 0 byte 01 half-word 10 word 11 reserved abttyp abort type 0 0 data read 0 1 data write 1 0 code fetch 11 reserved
92 at91sam7s64 preliminary 6070a?atarm?28-oct-04 svmst0: saved arm7tdmi abort source 0: no abort due to the arm7tdmi occurred since the last read of mc_asr or it is notified in the bit mst0. 1: at least one abort due to the arm7tdmi occurred since the last read of mc_asr. svmst1: saved pdc abort source 0: no abort due to the pdc occurred since the last read of mc_asr or it is notified in the bit mst1. 1: at least one abort due to the pdc occurred since the last read of mc_asr. mc abort address status register register name : mc_aasr access type : read-only reset value :0x0 offset :0x08 abtadd: abort address this field contains the address of the last aborted access. 31 30 29 28 27 26 25 24 abtadd 23 22 21 20 19 18 17 16 abtadd 15 14 13 12 11 10 9 8 abtadd 76543210 abtadd
93 at91sam7s64 preliminary 6070a?atarm?28-oct-04 embedded flash controller (efc) overview the embedded flash controller (efc) is a part of the memory controller and ensures the interface of the flash block with the 32-bit internal bus. it increases performance in thumb mode for code fetch with its system of 32-bit buffers. it also manages the programming, eras- ing, locking and unlocking sequences using a full set of commands. functional description embedded flash organization the embedded flash interfaces directly to the 32-bit internal bus. it is composed of several interfaces: one memory plane organized in several pages of the same size two 32-bit read buffers used for code read optimization. (see ?read operations? on page 95.) one write buffer that manages page programming. the write buffer size is equal to the page size. this buffer is write-only and accessible all along the 1 mbyte address space, so that each word can be written to its final address. (see ?write operations? on page 97.) several lock bits used to protect write and er ase operations on lock regions. a lock region is composed of several consecutive pages, and each lock region has its associated lock bit. several general-purpose nvm bits. each bit controls a specific feature in the device. refer to the product definition section to get the gp nvm assignment. the embedded flash size, the page size and the lock region organization are described in the product definition section.
94 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 31. embedded flash memory mapping lock region 0 lock region (n-1) page 0 page (m-1) start address 32-bit wide flash memory page ( (n-1)*m ) page (n*m-1) lock bit 0 lock region 1 lock bit 1 lock bit n-1
95 at91sam7s64 preliminary 6070a?atarm?28-oct-04 read operations an optimized controller manages embedded flash reads. a system of 2 x 32-bit buffers is added in order to start access at following address during the second read, thus increasing performance when the processor is running in thumb mode (16-bit instruction set). see fig- ure 32, figure 33 and figure 34. this optimization concerns only code fetch and not data. the read operations can be performed with or without wait state. up to 3 wait states can be programmed in the field fws (flash wait state) in the flash mode register mc_fmr (see ?mc flash mode register? on page 103). defining fws to be 0 enables the single-cycle access of the embedded flash. the flash memory is accessible through 8-, 16- and 32-bit reads. as the flash block size is smaller than the address space reserved for the internal memory area, the embedded flash wraps around the address space and appears to be repeated within it. figure 32. code read optimization in thumb mode for fws = 0 note: when fws is equal to 0, all accesses are performed in a single-cycle access. flash access buffer (32 bits) master clock a rm request (16-bit) code fetch data to arm bytes 0-3 bytes 4-7 bytes 0-3 bytes 0-1 bytes 2-3 bytes 4-5 bytes 6-7 bytes 8-9 bytes 10-11 bytes 12-13 @byte 0 @byte 2 @byte 4 @byte 6 @byte 8 @byte 10 @byte 12 @byte 14 @byte 16 bytes 14-15 bytes 4-7 bytes 8-11 bytes 8-11 bytes 12-15 bytes 16-19 bytes 12-15
96 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 33. code read optimization in thumb mode for fws = 1 note: when fws is equal to 1, in case of sequential reads, all the accesses are performed in a single-cycle access (except for t he first one). figure 34. code read optimization in thumb mode for fws = 3 note: when fws is equal to 2 or 3, in case of sequential reads, the first access takes fws cycles, the second access one cycle, the third access fws cycles, the fourth access one cycle, etc. flash access buffer (32 bits) master clock arm request (16-bit) code fetch data to arm bytes 0-3 bytes 4-7 bytes 0-3 bytes 2-3 bytes 4-5 bytes 6-7 bytes 8-9 bytes 10-11 @byte 0 @byte 4 @byte 6 @byte 8 @byte 10 @byte 12 @byte 14 bytes 4-7 bytes 8-11 bytes 8-11 bytes 12-15 1 wait state cycle bytes 0-1 1 wait state cycle 1 wait state cycle 1 wait state cycle @byte 2 bytes 12-13 flash access master clock data to arm 0-1 @byte 0 @2 bytes 0-3 bytes 4-7 bytes 8-11 bytes 12-15 bytes 0-3 2-3 6-7 @4 8-9 10-11 4-5 @8 @12 bytes 4-7 3 wait state cycles buffer (32 bits) arm request (16-bit) code fetch bytes 8-11 3 wait state cycles 3 wait state cycles 3 wait state cycles @6 @10 12-13
97 at91sam7s64 preliminary 6070a?atarm?28-oct-04 write operations the internal memory area reserved for the embedded flash can also be written through a write-only latch buffer. write operations take into account only the 8 lowest address bits and thus wrap around within the internal memory area address space and appear to be repeated 1024 times within it. write operations can be prevented by programming the memory protection unit of the product. writing 8-bit and 16-bit data is not allowed and may lead to unpredictable data fcorruption. write operations are performed in the number of wait states equal to the number of wait states for read operations + 1, except for fws = 3 (see ?mc flash mode register? on page 103). flash commands the embedded flash controller offers a command set to manage programming the memory flash, locking and unlocking lock sectors, consecutive programming and locking, and full flash erasing. to run one of these commands, the field fcmd of the mc_fcr register has to be written with the command number. as soon as the mc_fcr register is written, the frdy flag is automati- cally cleared. once the current command is achieved, then the frdy flag is automatically set. if an interrupt has been enabled by setting the bit frdy in mc_fmr, the interrupt line of the memory controller is activated. all the commands are protected by the same keyword, which has to be written in the eight highest bits of the mc_fcr register. writing mc_fcr with data that does not contain the correct key and/or with an invalid com- mand has no effect on the memory plane; however, the proge flag is set in the mc_fsr register. this flag is automatically cleared by a read access to the mc_fsr register. when the current command writes or erases a page in a locked region, the command has no effect on the whole memory plane; however, the flocke flag is set in the mc_fsr register. this flag is automatically cleared by a read access to the mc_fsr register. table 17. set of commands command value mnemonic write page 0x01 wp set lock bit 0x02 slb write page and lock 0x03 wpl clear lock bit 0x04 clb erase all 0x08 ea set general-purpose nvm bit 0x0b sgpb clear general-purpose nvm bit 0x0d cgpb set security bit 0x0f ssb
98 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 35. command statechart in order to guarantee valid operations on the flash memory, the field flash microsec- ond cycle number (fmcn) in the flash mode register mc_fmr must be correctly programmed (see ?mc flash mode register? on page 103). note: this field defines the number of master clock cycles in 1 microsecond that allow completion of some necessary internal timings. flash programming several commands can be used to program the flash. the flash technology requires that an erase must be done before programming. the entire memory plane can be erased at the same time, or a page can be automatically erased by clearing the nebp bit in the mc_fmr register before writing the command in the mc_fcr register. check if frdy flag set no yes read status: mc_fsr write fcmd and pagenb in mc_fcr check if locke flag set check if frdy flag set no read status: mc_fsr yes yes locking region violation no check if proge flag set yes no bad keyword violation and/or invalid command command successful
99 at91sam7s64 preliminary 6070a?atarm?28-oct-04 by setting the nebp bit in the mc_fmr register, a page can be programmed in several steps if it has been erased before (see figure 36). figure 36. example of partial page programming: after programming, the page (the whole lock region) can be locked to prevent miscellaneous write or erase sequences. the lock bit can be automatically set after page programming using wpl. data to be written are stored in an internal latch buffer. the size of the latch buffer corre- sponds to the page size. the latch buffer wraps around within the internal memory area address space and appears to be repeated by the number of pages in it. note: writing of 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption. data are written to the latch buffer before the programming command is written to the flash command register mc_fcr. the sequence is as follows: write the full page, at any page address, within the internal memory area address space using only 32-bit access. programming starts as soon as the page number and the programming command are written to the flash command register. the frdy bit in the flash programming status register (mc_fsr) is automatically cleared. when programming is completed, the bit frdy in the flash programming status register (mc_fsr) rises. if an interrupt was enabled by setting the bit frdy in mc_fmr, the interrupt line of the memory controller is activated. two errors can be detected in the mc_fsr register after a programming sequence: programming error: a bad keyword and/or an invalid command have been written in the mc_fcr register. lock error: the page to be programmed belongs to a locked region. a command must be previously run to unlock the corresponding region. erase all flash programming of the second part of page 7 programming of the third part of page 7 32 bits wide 32 bits wide 32 bits wide 16 words ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ... ca fe ca fe ca fe ca fe ca fe ca fe ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ca fe ca fe ca fe ca fe ca fe ca fe de ca de ca de ca de ca de ca de ca ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff step 1. step 2. step 3. ... ... ... ... ... ... ... ... ... ... ... (nebp = 1) (nebp = 1) 16 words 16 words 16 words page 7 erased
100 at91sam7s64 preliminary 6070a?atarm?28-oct-04 erase all command the entire memory can be erased if the erase all command (ea) in the flash command reg- ister mc_fcr is written. erase all operation is allowed only if there are no lock bits set. thus, if at least one lock region is locked, the bit locke in mc_fsr rises and the command is cancelled. if the bit locke has been written at 1 in mc_fmr, the interrupt line rises. when programming is complete, the bit frdy bit in the flash programming status register (mc_fsr) rises. if an interrupt has been enabled by setting the bit frdy in mc_fmr, the interrupt line of the memory controller is activated. two errors can be detected in the mc_fsr register after a programming sequence: programming error: a bad keyword and/or an invalid command have been written in the mc_fcr register. lock error: at least one lock region to be erased is protected. the erase command has been refused and no page has been erased. a clear lock bit command must be executed previously to unlock the corresponding lock regions. lock bit protection lock bits are associated with several pages in the embedded flash memory plane. this defines lock regions in the embedded flash memory plane. they prevent writing/erasing pro- tected pages. after production, the device may have some embedded flash lock regions locked. these locked regions are reserved for a default application. refer to the product definition section for the default embedded flash mapping. locked sectors can be unlocked to be erased and then programmed with another application or other data. the lock sequence is: the flash command register must be written with the following value: (0x5a << 24) | (lockpagenumber << 8 & pagen) | slb lockpagenumber is a page of the corresponding lock region. when locking completes, the bit frdy in the flash programming status register (mc_fsr) rises. if an interrupt has been enabled by setting the bit frdy in mc_fmr, the interrupt line of the memory controller is activated. a programming error, where a bad keyword and/or an invalid command have been written in the mc_fcr register, may be detected in the mc_fsr register after a programming sequence. it is possible to clear lock bits that were set previously. then the locked region can be erased or programmed. the unlock sequence is: the flash command register must be written with the following value: (0x5a << 24) | (lockpagenumber << 8 & pagen) | clb lockpagenumber is a page of the corresponding lock region. when the unlock completes, the bit frdy in the flash programming status register (mc_fsr) rises. if an interrupt has been enabled by setting the bit frdy in mc_fmr, the interrupt line of the memory controller is activated. a programming error, where a bad keyword and/or an invalid command have been written in the mc_fcr register, may be detected in the mc_fsr register after a programming sequence. the unlock command programs the lock bit to 1; the corresponding bit locksx in mc_fsr reads 0. the lock command programs the lock bit to 0; the corresponding bit locksx in mc_fsr reads 1. note: access to the flash in read mode is permitted when a lock or unlock command is performed.
101 at91sam7s64 preliminary 6070a?atarm?28-oct-04 general-purpose nvm bits general-purpose nvm bits do not interfere with the embedded flash memory plane. these general-purpose bits are dedicated to protect other parts of the product. they can be set (acti- vated) or cleared individually. refer to the product definition section for the general-purpose nvm bit action. the activation sequence is: start the set general purpose bit command (sgpb) by writing the flash command register with the sel command and the number of the general-purpose bit to be set in the pagen field. when the bit is set, the bit frdy in the flash programming status register (mc_fsr) rises. if an interrupt has been enabled by setting the bit frdy in mc_fmr, the interrupt line of the memory controller is activated. two errors can be detected in the mc_fsr register after a programming sequence: programming error: a bad keyword and/or an invalid command have been written in the mc_fcr register if the general-purpose bit number is greater than the total number of general-purpose bits, then the command has no effect. it is possible to deactivate a general-purpose nvm bit set previously. the clear sequence is: start the clear general-purpose bit command (cgpb) by writing the flash command register with cgpb and the number of the general-purpose bit to be cleared in the pagen field. when the clear completes, the bit frdy in the flash programming status register (mc_fsr) rises. if an interrupt has been enabled by setting the bit frdy in mc_fmr, the interrupt line of the memory controller is activated. two errors can be detected in the mc_fsr register after a programming sequence: programming error: a bad keyword and/or an invalid command have been written in the mc_fcr register if the number of the general-purpose bit set in the pagen field is greater than the total number of general-purpose bits, then the command has no effect. the clear general-purpose bit command programs the general-purpose nvm bit to 1; the cor- responding bit gpnvmx in mc_fsr reads 0. the set general-purpose bit command programs the general-purpose nvm bit to 0; the corresponding bit gpnvmx in mc_fsr reads 1. note: access to the flash in read mode is permitted when a set, clear or get general-purpose nvm bit command is performed. security bit the goal of the security bit is to prevent external access to the internal bus system. jtag, fast flash programming and flash serial test interface features are disabled. once set, this bit can be reset only by an external hardware erase request to the chip. refer to the product definition section for the pin name that controls the erase. in this case, the full memory plane is erased and all lock and general-purpose nvm bits are cleared. the security bit in the mc_fsr is cleared only after these operations. the activation sequence is: start the set security bit command (ssb) by writing the flash command register. when the locking completes, the bit frdy in the flash programming status register (mc_fsr) rises. if an interrupt has been enabled by setting the bit frdy in mc_fmr, the interrupt line of the memory controller is activated. when the security bit is active, th e security bit in the mc_fsr is set.
102 at91sam7s64 preliminary 6070a?atarm?28-oct-04 embedded flash controller (efc) user interface the user interface of the embedded flash controller is integrated within the memory controller. base address : 0xffff ff00 table 18. embedded flash controller (efc) register mapping offset register name access reset state 0x60 mc flash mode register mc_fmr read/write 0x0 0x64 mc flash command register mc_fcr write-only ? 0x68 mc flash status register mc_fsr read-only ? 0x6c reserved ? ? ?
103 at91sam7s64 preliminary 6070a?atarm?28-oct-04 mc flash mode register register name :mc_fmr access type : read/write offset :0x60 frdy: flash ready interrupt enable 0 = flash ready does not generate an interrupt. 1 = flash ready generates an interrupt. locke: lock error interrupt enable 0 = lock error does not generate an interrupt. 1 = lock error generates an interrupt. proge: programming error interrupt enable 0 = programming error does not generate an interrupt. 1 = programming error generates an interrupt. nebp: no erase before programming 0 = a page erase is performed before programming. 1 = no erase is performed before programming. fws: flash wait state this field defines the number of wait states for read and write operations: fmcn: flash microsecond cycle number this field defines the number of master clock cycles in 1 microsecond. warning : the value 0 is only allowed for a master clock period superior to 30 microseconds. warning: in order to guarantee valid operations on the flash memory, the field flash microsecond cycle number (fmcn) must be correctly programmed. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 fmcn 15 14 13 12 11 10 9 8 ?????? fws 76543210 nebp ? ? ? proge locke ? frdy fws read operations write operations 0 1 cycle 2 cycles 1 2 cycles 3 cycles 2 3 cycles 4 cycles 3 4 cycles 4 cycles
104 at91sam7s64 preliminary 6070a?atarm?28-oct-04 mc flash command register register name :mc_fcr access type : write-only offset :0x64 fcmd: flash command this field defines the flash commands: 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ?????? pagen 15 14 13 12 11 10 9 8 pagen 76543210 ???? fcmd fcmd operations 0000 no command. does not raise the programming error status flag in the flash status register mc_fsr. 0001 write page command (wp): starts the programming of the page specified in the pagen field. 0010 set lock bit command (slb): starts a set lock bit sequence of the lock region specified in the pagen field. 0011 write page and lock command (wpl): the lock sequence of the lock region associated with the page specified in the field pagen occurs automatically after completion of the programming sequence . 0100 clear lock bit command (clb): starts a clear lock bit sequence of the lock region specified in the pagen field. 1000 erase all command (ea): starts the erase of the entire flash. if at least one page is locked, the command is cancelled. 1011 set general-purpose nvm bit (sgpb): activates the general-purpose nvm bit corresponding to the number specified in the pagen field. 1101 clear general purpose nvm bit (cgpb): deactivates the general-purpose nvm bit corresponding to the number specified in the pagen field. 1111 set security bit command (ssb): sets security bit. others reserved. raises the programming error status flag in the flash status register mc_fsr.
105 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pagen: page number note: depending on the command, all the possible unused bits of pagen are meaningless. key: write protection key this field should be written with the value 0x5a to enable the command defined by the bits of the register. if the field is wri t- ten with a different value, the write is not performed and no action is started. command pagen description write page command pagen defines the page number to be written. write page and lock command pagen defines the page number to be written and its associated lock region. erase all command this field is meaningless set/clear lock bit command pagen defines one page number of the lock region to be locked or unlocked. set/clear general purpose nvm bit command pagen defines the general-purpose bit number. set security bit command this field is meaningless
106 at91sam7s64 preliminary 6070a?atarm?28-oct-04 mc flash status register register name :mc_fsr access type : read-only offset :0x68 frdy: flash ready status 0 = the embedded flash controller is busy and the application must wait before running a new command. 1 = the embedded flash controller is ready to run a new command. locke: lock error status 0 = no programming of at least one locked lock region has happened since the last read of mc_fsr. 1 = programming of at least one locked lock region has happened since the last read of mc_fsr. proge: programming error status 0 = no invalid commands and no bad keywords were written in the flash command register mc_fcr. 1 = an invalid command and/or a bad keyword was/were written in the flash command register mc_fcr. security: security bit status 0 = the security bit is disactive. 1 = the security bit is active. gpnvmx: general-purpose nvm bit status 0 = the corresponding general-purpose nvm bit is disactive. 1 = the corresponding general-purpose nvm bit is active. locksx: lock region x lock status 0 = the corresponding lock region is not locked. 1 = the corresponding lock region is locked. 31 30 29 28 27 26 25 24 locks15 locks14 locks13 locks12 locks11 locks10 locks9 locks8 23 22 21 20 19 18 17 16 locks7 locks6 locks5 locks4 locks3 locks2 locks1 locks0 15 14 13 12 11 10 9 8 ??????gpnvm1gpnvm0 76543210 ? ? ? security proge locke ? frdy
107 at91sam7s64 preliminary 6070a?atarm?28-oct-04 fast flash programming interface (ffpi) overview the fast flash programming interface provides two solutions - parallel or serial - for high-vol- ume programming using a standard gang programmer. the parallel interface is fully handshaked and the device is considered to be a standard eeprom. additi onally, the parallel protocol offers an optimized access to all the embedded flash functionalities. the serial inter- face uses the standard ieee 1149.1 jtag protocol. it offers an optimized access to all the embedded flash functionalities. although the fast flash programming mode is a dedicated mode for high volume program- ming, this mode is not designed for in-situ programming.
108 at91sam7s64 preliminary 6070a?atarm?28-oct-04 parallel fast flash programming device configuration in fast flash programming mode, the device is in a specific test mode. only a certain set of pins is significant. other pins must be left unconnected. figure 37. parallel programming interface ncmd pgmncmd rdy pgmrdy noe pgmnoe nvalid pgmnvalid mode[3:0] pgmm[3:0] data[15:0] pgmd[15:0] xin tst vddio pgmen0 pgmen1 0 - 50mhz vddio vddcore vddio vddpll vddflash gnd gnd vddio pgmen2 table 19. signal description list signal name function type active level comments power vddflash flash power supply power vddio i/o lines power supply power vddcore core power supply power vddpll backup i/o lines power supply power gnd ground ground clocks xin main clock input. this input can be tied to gnd. in this case, the device is clocked by the internal rc oscillator. input 32khz to 50mhz test tst test mode select input high must be connected to vddio pgmen0 test mode select input high must be connected to vddio pgmen1 test mode select input high must be connected to vddio pgmen2 test mode select input low must be connected to gnd
109 at91sam7s64 preliminary 6070a?atarm?28-oct-04 signal names depending on the mode settings, data is latched in different internal registers. when mode is equal to cmde, then a new command (strobed on data[15:0] signals) is stored in the command register. pio pgmncmd valid command available input low pulled-up input at reset pgmrdy 0: device is busy 1: device is ready for a new command output high pulled-up input at reset pgmnoe output enable (active high) input low pulled-up input at reset pgmnvalid 0: data[15:0] is in input mode 1: data[15:0] is in output mode output low pulled-up input at reset pgmm[3:0] specifies data type (see table 20) input pulled-up input at reset pgmd[15:0] bi-directional data bus input/output pulled-up input at reset table 19. signal description list (continued) signal name function type active level comments table 20. mode coding mode[3:0] symbol data 0000 cmde command register 0001 addr0 address register lsbs 0010 addr1 0011 addr2 0100 addr2 address register msbs 0101 data data register default idle no register table 21. command bit coding data[15:0] symbol command executed 0x0011 read read flash 0x0012 wp write page flash 0x0022 wpl write page and lock flash 0x0032 ewp erase page and write page 0x0042 ewpl erase page and write page then lock 0x0013 ea erase all 0x0014 slb set lock bit 0x0024 clb clear lock bit 0x0015 glb get lock bit 0x0034 sfb set general purpose nvm bit 0x0044 cfb clear general purpose nvm bit 0x0025 gfb get general purpose nvm bit
110 at91sam7s64 preliminary 6070a?atarm?28-oct-04 entering programming mode the following algorithm puts the device in parallel programming mode: apply gnd, vddio, vddcore, vddflash and vddpll. apply xin clock within t por_reset if an external clock is available. wait for t por_reset start a read or write handshaking. note: after reset, the device is clocked by the internal rc oscillator. before clearing rdy signal, if an external clock ( > 32 khz) is connected to xin, then the device switches on the external clock. else, xin input is not considered. a higher frequency on xin speeds up the programmer handshake. programmer handshaking an handshake is defined for read and write operations. when the device is ready to start a new operation (rdy signal set), the programmer starts the handshake by clearing the ncmd signal. the handshaking is achieved once ncmd signal is high and rdy is high. write handshaking for details on the write handshaking sequence, refer to figure 38 and table 22. figure 38. parallel programming timing, write sequence 0x0054 sse set security bit 0x0035 gse get security bit 0x001e gve get version table 21. command bit coding (continued) data[15:0] symbol command executed ncmd rdy noe nvalid data[15:0] mode[3:0] 1 2 3 4 5 table 22. write handshake step programmer action device action data i/o 1 sets mode and data signals waits for ncmd low input 2 clears ncmd signal latches mode and data input 3 waits for rdy low clears rdy signal input
111 at91sam7s64 preliminary 6070a?atarm?28-oct-04 read handshaking for details on the read handshaking sequence, refer to figure 39 and table 23. figure 39. parallel programming timing, read sequence 4 releases mode and data signals executes command and polls ncmd high input 5 sets ncmd signal executes command and polls ncmd high input 6 waits for rdy high sets rdy input table 22. write handshake (continued) step programmer action device action data i/o ncmd rdy noe nvalid data[15:0] mode[3:0] 1 2 3 4 5 6 7 9 8 addr adress in z data out 10 11 xin 12 13 table 23. read handshake step programmer action device action data i/o 1 sets mode and data signals waits for ncmd low input 2 clears ncmd signal latch mode and data input 3 waits for rdy low clears rdy signal input 4 sets data signal in tristate waits for noe low input 5 clears noe signal tristate 6 waits for nvalid low sets data bus in output mode and outputs the flash contents. output 7 clears nvalid signal output 8 reads value on data bus waits for noe high output 9 sets noe signal output 10 waits for nvalid high sets data bus in input mode x 11 sets data in ouput mode sets nvalid signal input 12 sets ncmd signal waits for ncmd high input 13 waits for rdy high sets rdy signal input
112 at91sam7s64 preliminary 6070a?atarm?28-oct-04 device operations several commands on the flash memory are available. these commands are summarized in table 21 on page 109. each command is driven by the programmer through the parallel inter- face running several read/write handshaking sequences. when a new command is executed, the previous one is automatically achieved. thus, chain- ing a read command after a write automatically flushes the load buffer in the flash. flash read command this command is used to read the contents of the flash memory. the read command can start at any valid address in the memory plane and is optimized for consecutive reads. read hand- shaking can be chained; an internal address buffer is automatically increased. flash write command this command is used to write the flash contents. the flash memory plane is organized into several pages. data to be written are stored in a load buffer that corresponds to a flash memory page. the load buffer is automatically flushed to the flash: before access to any page other than the current one when a new command is validated (mode = cmde) the write page command (wp) is optimized for consecutive writes. write handshaking can be chained; an internal address buffer is automatically increased. table 24. read command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde read 2 write handshaking addr0 32-bit memory address first byte 3 write handshaking addr1 32-bit flash address 4 write handshaking addr2 32-bit flash address 5 write handshaking addr3 32-bit flash address last byte 6 read handshaking data *memory address++ 7 read handshaking data *memory address++ ... ... ... ... n write handshaking addr0 32-bit memory address first byte n+1 write handshaking addr1 32-bit flash address n+2 write handshaking addr2 32-bit flash address n+3 write handshaking addr3 32-bit flash address last byte n+4 read handshaking data *memory address++ n+5 read handshaking data *memory address++ ... ... ... ... table 25. write command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde wp or wpl or ewp or ewpl 2 write handshaking addr0 32-bit memory address first byte 3 write handshaking addr1 32-bit flash address 4 write handshaking addr2 32-bit flash address
113 at91sam7s64 preliminary 6070a?atarm?28-oct-04 the flash command write page and lock (wpl) is equivalent to the flash write command. however, the lock bit is automatically set at the end of the flash write operation. as a lock region is composed of several pages, the programmer writes to the first pages of the lock region using flash write commands and writes to the last page of the lock region using a flash write and lock command. the flash command erase page and write (ewp) is equivalent to the flash write com- mand. however, before programming the load buffer, the page is erased. the flash command erase page and write the lock (ewpl) combines ewp and wpl commands. flash full erase command this command is used to erase the flash memory planes. all lock regions must be unlocked before the full erase command by using the clb com- mand. otherwise, the erase command is aborted and no page is erased. 5 write handshaking addr3 32-bit flash address last byte 6 write handshaking data *memory address++ 7 write handshaking data *memory address++ ... ... ... ... n write handshaking addr0 32-bit memory address first byte n+1 write handshaking addr1 32-bit flash address n+2 write handshaking addr2 32-bit flash address n+3 write handshaking addr3 32-bit flash address last byte n+4 write handshaking data *memory address++ n+5 write handshaking data *memory address++ ... ... ... ... table 25. write command (continued) step handshake sequence mode[3:0] data[15:0] table 26. full erase command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde ea 2 write handshaking data 0
114 at91sam7s64 preliminary 6070a?atarm?28-oct-04 flash lock commands lock bits can be set using wpl or ewpl commands. they can also be set by using the set lock command (slb) . with this command, several lock bits can be activated. a bit mask is provided as argument to the command. when bit 0 of the bit mask is set, then the first lock bit is activated. in the same way, the clear lock command (clb) is used to clear lock bits. all the lock bits are also cleared by the ea command. lock bits can be read using get lock bit command (glb) . the n th lock bit is active when the bit n of the bit mask is set.. flash general purpose nvm commands general-purpose nvm bits (gp nvm bits) can be set using the set fuse command (sfb) . this command also activates gp nvm bits. a bit mask is provided as argument to the com- mand. when bit 0 of the bit mask is set, then the first gp nvm bit is activated. in the same way, the clear fuse command (cfb) is used to clear general-purpose nvm bits. all the general-purpose nvm bits are also cleared by the ea command. the general-purpose nvm bit is deactived when the corresponding bit in the pattern value is set to 1. general-purpose nvm bits can be read using the get fuse bit command (gfb) . the n th gp nvm bit is active when bit n of the bit mask is set.. table 27. set and clear lock bit command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde slb or clb 2 write handshaking data bit mask table 28. get lock bit command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde glb 2 read handshaking data lock bit mask status 0 = lock bit is cleared 1 = lock bit is set table 29. set/clear gp nvm command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde sfb or cfb 2 write handshaking data gp nvm bit pattern value table 30. get gp nvm bit command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde gfb 2 read handshaking data gp nvm bit mask status 0 = gp nvm bit is cleared 1 = gp nvm bit is set
115 at91sam7s64 preliminary 6070a?atarm?28-oct-04 flash security bit command a security bit can be set using the set security bit command (sse). once the security bit is active, the fast flash programming is disabled. no other command can be run. an event on the erase pin can erase the security bit once the contents of the flash have been erased. get version command the get version (gve) command retrieves the version of the ffpi interface. table 31. set security bit command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde sse 2 write handshaking data 0 table 32. get version command step handshake sequence mode[3:0] data[15:0] 1 write handshaking cmde gve 2 write handshaking data version
116 at91sam7s64 preliminary 6070a?atarm?28-oct-04 serial fast flash programming the serial fast flash programming interface is based on ieee std. 1149.1 ?standard test access port and boundary-scan architecture?. refer to this standard for an explanation of terms used in this chapter and for a description of the tap controller states. in this mode, data read/written from/to the embedded flash of the device are transmitted through the jtag interface of the device. device configuration in serial fast flash programming mode, the device is in a specific test mode. only a distinct set of pins is significant. other pins must be left unconnected. figure 40. serial programming tdi tdo tms tck xin tst vddio pgmen0 pgmen1 0-50mhz vddio vddcore vddio vddpll vddflash gnd vddio gnd pgmen2 table 33. signal description list signal name function type active level comments power vddflash flash power supply power vddio i/o lines power supply power vddcore core power supply power vddpll backup i/o lines power supply power gnd ground ground clocks xin main clock input. this input can be tied to gnd. in this case, the device is clocked by the internal rc oscillator. input 32 khz to 50 mhz
117 at91sam7s64 preliminary 6070a?atarm?28-oct-04 entering serial programming mode the following algorithm puts the device in serial programming mode: apply gnd, vddio, vddcore, vddflash and vddpll. apply xin clock within t por_reset + 32(t sclk ) if an external clock is available. wait for t por_reset . reset the tap controller clocking 5 tck pulses with tms set. shift 0x2 into the ir register ( ir is 4 bits long, lsb first) without going through the run- test-idle state. shift 0x2 into the dr register ( dr is 4 bits long, lsb first) without going through the run- test-idle state. shift 0xc into the ir register ( ir is 4 bits long, lsb first) without going through the run- test-idle state. note: after reset, the device is clocked by the internal rc oscillator. before clearing rdy signal, if an external clock ( > 32 khz) is connected to xin, then the device will switch on the external clock. else, xin input is not considered. an higher frequency on xin speeds up the programmer handshake. read/write handshake two registers of the device are accessible through the jtag: debug comms control register: dccr debug comms data register: dcdr test tst test mode select input high must be connected to vddio. pgmen0 test mode select input high must be connected to vddio pgmen1 test mode select input high must be connected to vddio pgmen2 test mode select input low must be connected to gnd jtag tck jtag tck input - pulled-up input at reset tdi jtag test data in input - pulled-up input at reset tdo jtag test data out output - tms jtag test mode select input - pulled-up input at reset table 33. signal description list (continued) signal name function type active level comments table 34. reset tap controller and go to select-dr-scan tdi tms tap controller state x1 x1 x1 x1 x 1 test-logic reset x 0 run-test/idle xt 1 select-dr-scan
118 at91sam7s64 preliminary 6070a?atarm?28-oct-04 access to these registers is done through the tap 38-bit dr register comprising a 32-bit data field, a 5-bit address field and a read/write bit. the data to be written is scanned into the 32-bit data field with the address of the register to the 5-bit address field and 1 to the read/write bit. a register is read by scanning its address into the address field and 0 into the read/write bit, going through the update-dr tap state, then scanning out the data. the 32-bit data field is ignored. figure 41. tap 8-bit dr register a read or write takes place when the tap controller enters update-dr state. the address of the debug comms control register is 0x04. the address of the debug comms data register is 0x05. the debug comms control register is read-only and allows synchronized handshaking between the processor and the debugger. bit 1 (w): denotes whether the programmer can read a data through the debug comms data register. if the device is busy w = 0, then the programmer must poll until w = 1. bit 0 (r): denotes whether the programme r can send data from the debug comms data register. if r = 1, data previously placed there through the scan chain has not been collected by the device and so the programmer must wait. device operations several commands on the flash memory are available. these commands are summarized in table 21 on page 109. commands are run by the programmer through the serial interface that is reading and writing the debug comms registers. flash read command this command is used to read the flash contents. the memory map is accessible through this command. memory is seen as an array of words (32-bit wide). the read command can start at any valid address in the memory plane. this address must be word-aligned . the address is automatically incremented. tdi tdo 4 0 r/w address 31 data 0 address decoder debug comms control register debug comms control register 32 5 table 35. read command read/write dr data write (number of words to read) << 16 | read write address read memory [address] read memory [address+4] ... ... read memory [address+(number of words to read - 1)* 4]
119 at91sam7s64 preliminary 6070a?atarm?28-oct-04 flash write command this command is used to write the flash contents. the address transmitted must be a valid flash address in the memory plane. the flash memory plane is organized into several pages. data to be written is stored in a load buffer that corresponds to a flash memory page. the load buffer is automatically flushed to the flash: before access to any page than the current one at the end of the number of words transmitted the write page command (wp) is optimized for consecutive writes. write handshaking can be chained; an internal address buffer is automatically increased. flash write page and lock command (wpl) is equivalent to the flash write command. however, the lock bit is automatically set at the end of the flash write operation. as a lock region is composed of several pages, the programmer writes to the first pages of the lock region using flash write commands and writes to the last page of the lock region using a flash write and lock command. flash erase page and write command (ewp) is equivalent to the flash write command. however, before programming the load buffer, the page is erased. flash erase page and write the lock command (ewpl) combines ewp and wpl commands. flash full erase command this command is used to erase the flash memory planes. all lock bits must be deactivated before using the full erase command. this can be done by using the clb command. flash lock commands lock bits can be set using wpl or ewpl commands. they can also be set by using the set lock command (slb) . with this command, several lock bits can be activated at the same time. bit 0 of bit mask corresponds to the first lock bit and so on. in the same way, the clear lock command (clb) is used to clear lock bits. all the lock bits can also be cleared by the ea command. table 36. write command read/write dr data write (number of words to write) << 16 | (wp or wpl or ewp or ewpl) write address write memory [address] write memory [address+4] write memory [address+8] write memory [address+(number of words to write - 1)* 4] table 37. full erase command read/write dr data write ea
120 at91sam7s64 preliminary 6070a?atarm?28-oct-04 lock bits can be read using get lock bit command (glb) . when a bit set in the bit mask is returned, then the corresponding lock bit is active. flash general- purpose nvm commands general-purpose nvm bits (gp nvm) can be set with the set fuse command (sfb) . using this command, several gp nvm bits can be activated at the same time. bit 0 of bit mask cor- responds to the first fuse bit and so on. in the same way, the clear fuse command (cfb) is used to clear gp nvm bits. all the gen- eral-purpose nvm bits are also cleared by the ea command. gp nvm bits can be read using get fuse bit command (gfb) . when a bit set in the bit mask is returned, then the corresponding fuse bit is set. flash security bit command security bits can be set using set security bit command (sse). once the security bit is active, the fast flash programming is disabled. no other command can be run. only an event on the erase pin can erase the security bit once the contents of the flash have been erased. get version command the get version (gve) command retrieves the version of the ffpi interface. table 38. set and clear lock bit command read/write dr data write slb or clb write bit mask table 39. get lock bit command read/write dr data write glb read bit mask table 40. set and clear general-purpose nvm bit command read/write dr data write sfb or cfb write bit mask table 41. get general-purpose nvm bit command read/write dr data write gfb read bit mask table 42. set security bit command read/write dr data write sse table 43. get version command read/write dr data write gve read version
121 at91sam7s64 preliminary 6070a?atarm?28-oct-04 peripheral data controller (pdc) overview the peripheral data controller (pdc) transfers data between on-chip serial peripherals such as the uart, usart, ssc, spi, mci and the on- and off-chip memories. using the periph- eral data contoller avoids processor intervention and removes the processor interrupt- handling overhead. this significantly reduces the number of clock cycles required for a data transfer and, as a result, improves the performance of the microcontroller and makes it more power efficient. the pdc channels are implemented in pairs, each pair being dedicated to a particular periph- eral. one channel in the pair is dedicated to the receiving channel and one to the transmitting channel of each uart, usart, ssc and spi. the user interface of a pdc channel is integrated in the memory space of each peripheral. it contains: a 32-bit memory pointer register a 16-bit transfer count register a 32-bit register for next memory pointer a 16-bit register for next transfer count the peripheral triggers pdc transfers using transmit and receive signals. when the pro- grammed data is transferred, an end of transfer interrupt is generated by the corresponding peripheral. block diagram figure 42. block diagram control pdc channel 0 pdc channel 1 thr rhr control status & control peripheral peripheral data controller memory controller
122 at91sam7s64 preliminary 6070a?atarm?28-oct-04 functional description configuration the pdc channels user interface enables the user to configure and control the data transfers for each channel. the user interface of a pdc channel is integrated into the user interface of the peripheral (offset 0x100), which it is related to. per peripheral, it contains four 32-bit pointer registers (rpr, rnpr, tpr, and tnpr) and four 16-bit counter registers (rcr, rncr, tcr, and tncr). the size of the buffer (number of transfers) is configured in an internal 16-bit transfer counter register, and it is possible, at any moment, to read the number of transfers left for each channel. the memory base address is configured in a 32-bit memory pointer by defining the location of the first address to access in the memory. it is possible, at any moment, to read the location in memory of the next transfer and the number of remaining transfers. the pdc has dedicated status registers which indicate if the transfer is enabled or disabled for each channel. the sta- tus for each channel is located in the peripheral status register. transfers can be enabled and/or disabled by setting txten/txtdis and rxten/rxtdis in pdc transfer control register. these control bits enable reading the pointer and counter registers safely without any risk of their changing between both reads. the pdc sends status flags to the peripheral visible in its status-register (endrx, endtx, rxbuff, and txbufe). endrx flag is set when the periph_rcr register reaches zero. rxbuff flag is set when both periph_rcr and periph_rncr reach zero. endtx flag is set when the periph_tcr register reaches zero. txbufe flag is set when both periph_tcr and periph_tncr reach zero. these status flags are described in the peripheral status register. memory pointers each peripheral is connected to the pdc by a receiver data channel and a transmitter data channel. each channel has an internal 32-bit memory pointer. each memory pointer points to a location anywhere in the memory space (on-chip memory or external bus interface memory). depending on the type of transfer (byte, half-word or word), the memory pointer is incre- mented by 1, 2 or 4, respectively for peripheral transfers. if a memory pointer is reprogrammed while the pdc is in operation, the transfer address is changed, and the pdc performs transfers using the new address. transfer counters there is one internal 16-bit transfer counter for each channel used to count the size of the block already transferred by its associated channel. these counters are decremented after each data transfer. when the counter reaches zero, the transfer is complete and the pdc stops transferring data. if the next counter register is equal to zero, the pdc disables the trigger while activating the related peripheral end flag. if the counter is reprogrammed while the pdc is operating, the number of transfers is updated and the pdc counts transfers from the new value. programming the next counter/pointer registers chains the buffers. the counters are decre- mented after each data transfer as stated above, but when the transfer counter reaches zero,
123 at91sam7s64 preliminary 6070a?atarm?28-oct-04 the values of the next counter/pointer are loaded into the counter/pointer registers in order to re-enable the triggers. for each channel, two status bits indicate the end of the current buffer (endrx, entx) and the end of both current and next buffer (rxbuff, txbufe). these bits are directly mapped to the peripheral status register and can trigger an interrupt request to the aic. the peripheral end flag is automatically cleared when one of the counter-registers (counter or next counter register) is written. note: when the next counter register is loaded into the counter register, it is set to zero. data transfers the peripheral triggers pdc transfers using transmit (txrdy) and receive (rxrdy) signals. when the peripheral receives an external character, it sends a receive ready signal to the pdc which then requests access to the system bus. when access is granted, the pdc starts a read of the peripheral receive holding regi ster (rhr) and then triggers a write in the memory. after each transfer, the relevant pdc memory pointer is incremented and the number of trans- fers left is decremented. when the memory block size is reached, a signal is sent to the peripheral and the transfer stops. the same procedure is followed, in reverse, for transmit transfers. priority of pdc transfer requests the peripheral data controller handles transfer requests from the channel according to priori- ties fixed for each product.these priorities are defined in the product datasheet. if simultaneous requests of the same type (receiver or transmitter) occur on identical peripher- als, the priority is determined by the numbering of the peripherals. if transfer requests are not simultaneous, they are treated in the order they occurred. requests from the receivers are handled first and then followed by transmitter requests.
124 at91sam7s64 preliminary 6070a?atarm?28-oct-04 peripheral data controller (pdc) user interface note: 1. periph: ten registers are mapped in the peripheral memory space at the same offset. these can be defined by the user according to the function and the peripheral desired (dbgu, usart, ssc, spi, mci etc). table 44. peripheral data controller (pdc) register mapping offset register register name read/write reset 0x100 receive pointer register periph (1) _rpr read/write 0x0 0x104 receive counter register periph_rcr read/write 0x0 0x108 transmit pointer register periph_tpr read/write 0x0 0x10c transmit counter register periph_tcr read/write 0x0 0x110 receive next pointer register periph_rnpr read/write 0x0 0x114 receive next counter register periph_rncr read/write 0x0 0x118 transmit next pointer register periph_tnpr read/write 0x0 0x11c transmit next counter register periph_tncr read/write 0x0 0x120 pdc transfer control register periph_ptcr write-only - 0x124 pdc transfer status register periph_ptsr read-only 0x0
125 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pdc receive pointer register register name: periph _ rpr access type: read/write rxptr: receive pointer address address of the next receive transfer. pdc receive counter register register name: periph _ rcr access type: read/write rxctr: receive counter value number of receive transfers to be performed. 31 30 29 28 27 26 25 24 rxptr 23 22 21 20 19 18 17 16 rxptr 15 14 13 12 11 10 9 8 rxptr 76543210 rxptr 31 30 29 28 27 26 25 24 -- 23 22 21 20 19 18 17 16 -- 15 14 13 12 11 10 9 8 rxctr 76543210 rxctr
126 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pdc transmit pointer register register name: periph _ tpr access type: read/write txptr: transmit pointer address address of the transmit buffer. pdc transmit counter register register name: periph _ tcr access type: read/write txctr: transmit counter value txctr is the size of the transmit transfer to be performed. at zero, the peripheral data transfer is stopped. 31 30 29 28 27 26 25 24 txptr 23 22 21 20 19 18 17 16 txptr 15 14 13 12 11 10 9 8 txptr 76543210 txptr 31 30 29 28 27 26 25 24 -- 23 22 21 20 19 18 17 16 -- 15 14 13 12 11 10 9 8 txctr 76543210 txctr
127 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pdc receive next pointer register register name: periph _ rnpr access type: read/write rxnptr: receive next pointer address rxnptr is the address of the next buffer to fill with received data when the current buffer is full. pdc receive next counter register register name: periph _ rncr access type: read/write rxncr: receive next counter value rxncr is the size of the next buffer to receive. 31 30 29 28 27 26 25 24 rxnptr 23 22 21 20 19 18 17 16 rxnptr 15 14 13 12 11 10 9 8 rxnptr 76543210 rxnptr 31 30 29 28 27 26 25 24 -- 23 22 21 20 19 18 17 16 -- 15 14 13 12 11 10 9 8 rxncr 76543210 rxncr
128 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pdc transmit next pointer register register name: periph _ tnpr access type: read/write txnptr: transmit next pointer address txnptr is the address of the next buffer to transmit when the current buffer is empty. pdc transmit next counter register register name: periph _ tncr access type: read/write txncr: transmit next counter value txncr is the size of the next buffer to transmit. 31 30 29 28 27 26 25 24 txnptr 23 22 21 20 19 18 17 16 txnptr 15 14 13 12 11 10 9 8 txnptr 76543210 txnptr 31 30 29 28 27 26 25 24 -- 23 22 21 20 19 18 17 16 -- 15 14 13 12 11 10 9 8 txncr 76543210 txncr
129 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pdc transfer control register register name: periph_ptcr access type: write - only rxten: receiver transfer enable 0 = no effect. 1 = enables the receiver pdc transfer requests if rxtdis is not set. rxtdis: receiver transfer disable 0 = no effect. 1 = disables the receiver pdc transfer requests. txten: transmitter transfer enable 0 = no effect. 1 = enables the transmitter pdc transfer requests. txtdis: transmitter transfer disable 0 = no effect. 1 = disables the transmitter pdc transfer requests 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????txtdistxten 76543210 ??????rxtdisrxten
130 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pdc transfer status register register name: periph _ ptsr access type: read-only rxten: receiver transfer enable 0 = receiver pdc transfer requests are disabled. 1 = receiver pdc transfer requests are enabled. txten: transmitter transfer enable 0 = transmitter pdc transfer requests are disabled. 1 = transmitter pdc transfer requests are enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????txten 76543210 ???????rxten
131 at91sam7s64 preliminary 6070a?atarm?28-oct-04 advanced interrupt controller (aic) overview the advanced interrupt controller (aic) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. it is designed to substantially reduce the software and real-time overhead in handling internal and external interrupts. the aic drives the nfiq (fast interrupt request) and the nirq (standard interrupt request) inputs of an arm processor. inputs of the aic are either internal peripheral interrupts or exter- nal interrupts coming from the product's pins. the 8-level priority controller allows the user to define the priority for each interrupt source, thus permitting higher priority interrupts to be serviced even if a lower priority interrupt is being treated. internal interrupt sources can be programmed to be level sensitive or edge triggered. external interrupt sources can be programmed to be positive-edge or negative-edge triggered or high- level or low-level sensitive. the fast forcing feature redirects any internal or external interrupt source to provide a fast interrupt rather than a normal interrupt. block diagram figure 43. block diagram application block diagram figure 44. description of the application block aic apb arm processor fiq irq0-irqn embedded peripheralee peripheral embedded peripheral embedded up to thirty-two sources nfiq nirq advanced interrupt controller embedded peripherals external peripherals (external interrupts) standalone applications rtos drivers hard real time tasks os-based applications os drivers general os interrupt handler
132 at91sam7s64 preliminary 6070a?atarm?28-oct-04 aic detailed block diagram figure 45. aic detailed block diagram i/o line description product dependencies i/o lines the interrupt signals fiq and irq0 to irqn are normally multiplexed through the pio control- lers. depending on the features of the pio controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. this is not applicable when the pio controller used in the product is transparent on the input path. power management the advanced interrupt controller is continuously clocked. the power management controller has no effect on the advanced interrupt controller behavior. the assertion of the advanced interrupt controller outputs, either nirq or nfiq, wakes up the arm processor while it is in idle mode. the general interrupt mask feature enables the aic to wake up the processor without asserting the interrupt line of the processor, thus providing syn- chronization of the processor on an event. interrupt sources the interrupt source 0 is always located at fiq. if the product does not feature an fiq pin, the interrupt source 0 cannot be used. the interrupt source 1 is always located at system interrupt. this is the result of the or-wir- ing of the system peripheral interrupt lines, such as the system timer, the real time clock, the power management controller and the memory controller. when a system interrupt fiq pio controller advanced interrupt controller irq0-irqn pioirq embedded peripherals external source input stage internal source input stage fast forcing interrupt priority controller fast interrupt controller arm processor nfiq nirq power management controller wake up user interface apb processor clock table 45. i/o line description pin name pin description type fiq fast interrupt input irq0 - irqn interrupt 0 - interrupt n input
133 at91sam7s64 preliminary 6070a?atarm?28-oct-04 occurs, the service routine must first distinguish the cause of the interrupt. this is performed by reading successively the status registers of the above mentioned system peripherals. the interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to external interrupt lines. the external interrupt lines can be connected directly, or through the pio controller. the pio controllers are considered as user peripherals in the scope of interrupt handling. accordingly, the pio controller interrupt lines are connected to the interrupt sources 2 to 31. the peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peripheral). consequently, to simplify the description of the functional operations and the user interface, the interrupt sources are named fiq, sys, and pid2 to pid31.
134 at91sam7s64 preliminary 6070a?atarm?28-oct-04 functional description interrupt source control interrupt source mode the advanced interrupt controller independently programs each interrupt source. the src- type field of the corresponding aic_smr (source mode register) selects the interrupt condition of each source. the internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode. the active level of the internal interrupts is not important for the user. the external interrupt sources can be programmed either in high level-sensitive or low level- sensitive modes, or in positive edge-triggered or negative edge-triggered modes. interrupt source enabling each interrupt source, including the fiq in source 0, can be enabled or disabled by using the command registers; aic_iecr (interrupt enable command register) and aic_idcr (inter- rupt disable command register). this set of registers conducts enabling or disabling in one instruction. the interrupt mask can be read in the aic_imr register. a disabled interrupt does not affect servicing of other interrupts. interrupt clearing and setting all interrupt sources programmed to be edge-tr iggered (including the fiq in source 0) can be individually set or cleared by writing respectively the aic_iscr and aic_iccr registers. clearing or setting interrupt sources programmed in level-sensitive mode has no effect. the clear operation is perfunctory, as the software must perform an action to reinitialize the ?memorization? circuitry activated when the source is programmed in edge-triggered mode. however, the set operation is available for auto-test or software debug purposes. it can also be used to execute an aic-implementation of a software interrupt. the aic features an automatic clear of the current interrupt when the aic_ivr (interrupt vec- tor register) is read. only the interrupt source being detected by the aic as the current interrupt is affected by this operation. (see ?priority controller? on page 137.) the automatic clear reduces the operations required by the interrupt service routine entry code to reading the aic_ivr. note that the automatic interrupt clear is disabled if the interrupt source has the fast forcing feature enabled as it is considered uniquely as a fiq source. (for further details, see ?fast forcing? on page 141.) the automatic clear of the interrupt source 0 is performed when aic_fvr is read. interrupt status for each interrupt, the aic operation originates in aic_ipr (interrupt pending register) and its mask in aic_imr (interrupt mask register). aic_ipr enables the actual activity of the sources, whether masked or not. the aic_isr register reads the number of the current interrupt (see ?priority controller? on page 137) and the register aic_cisr gives an image of the signals nirq and nfiq driven on the processor. each status referred to above can be used to optimize the interrupt handling of the systems.
135 at91sam7s64 preliminary 6070a?atarm?28-oct-04 internal interrupt source input stage figure 46. internal interrupt source input stage external interrupt source input stage figure 47. external interrupt source input stage edge detector clear set source i aic_ipr aic_imr aic_iecr aic_idcr aic_iscr aic_iccr fast interrupt controller or priority controller ff level/ edge aic_smri (srctype) edge detector clear set pos./neg. aic_iscr aic_iccr source i ff level/ edge high/low aic_smri srctype aic_ipr aic_imr aic_iecr aic_idcr fast interrupt controller or priority controller
136 at91sam7s64 preliminary 6070a?atarm?28-oct-04 interrupt latencies global interrupt latencies depend on several parameters, including: the time the software masks the interrupts. occurrence, either at the processor level or at the aic level. the execution time of the instruction in progress when the interrupt occurs. the treatment of higher priority interrupt s and the resynchronization of the hardware signals. this section addresses only the hardware resynchronizations. it gives details of the latency times between the event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nirq or nfiq line on the processor. the resynchronization time depends on the programming of the interrupt source and on its type (internal or external). for the standard interrupt, resynchronization times are given assuming there is no higher priority in progress. the pio controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. external interrupt edge triggered source figure 48. external interrupt edge triggered source external interrupt level sensitive source figure 49. external interrupt level sensitive source maximum fiq latency = 4 cycles maximum irq latency = 4 cycles nfiq nirq mck irq or fiq (positive edge) irq or fiq (negative edge) maximum irq latency = 3 cycles maximum fiq latency = 3 cycles mck irq or fiq (high level) irq or fiq (low level) nirq nfiq
137 at91sam7s64 preliminary 6070a?atarm?28-oct-04 internal interrupt edge triggered source figure 50. internal interrupt edge triggered source internal interrupt level sensitive source figure 51. internal interrupt level sensitive source normal interrupt priority controller an 8-level priority controller drives the nirq line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in fast forcing). each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writing the prior field of the corresponding aic_smr (source mode register). level 7 is the highest priority and level 0 the lowest. as soon as an interrupt condition occurs, as defined by the srctype field of the aic_svr (source vector register), the nirq line is asserted. as a new interrupt condition might have happened on other interrupt sources since the nirq has been asserted, the priority controller determines the current interrupt at the time the aic_ivr (interrupt vector register) is read. the read of aic_ivr is the entry point of the interrupt handling which allows the aic to consider that the interrupt has been taken into account by the software. the current priority level is defined as the priority level of the current interrupt. if several interrupt sources of equal priority are pending and enabled when the aic_ivr is read, the interrupt with the lowest interrupt source number is serviced first. the nirq line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority. if an interrupt condition happens (or is pending) during the interrupt treatment in progress, it is delayed until the software indicates to the aic the end of the current service by writing the aic_eoicr (end of interrupt command register). the write of aic_eoicr is the exit point of the interrupt handling . mck nirq peripheral interrupt becomes active maximum irq latency = 4.5 cycles mck nirq maximum irq latency = 3.5 cycles peripheral interrupt becomes active
138 at91sam7s64 preliminary 6070a?atarm?28-oct-04 interrupt nesting the priority controller utilizes interrupt nesting in order for the high priority interrupt to be han- dled during the service of lower priority interrupts. this requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level. when an interrupt of a higher priority happens during an already occurring interrupt service routine, the nirq line is re-asserted. if the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service routine should read the aic_ivr. at this time, the current interrupt number and its priority level are pushed into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is fin- ished and the aic_eoicr is written. the aic is equipped with an 8-level wide hardware stack in order to support up to eight inter- rupt nestings pursuant to having eight priority levels. interrupt vectoring the interrupt handler addresses corresponding to each interrupt source can be stored in the registers aic_svr1 to aic_svr31 (source vector register 1 to 31). when the processor reads aic_ivr (interrupt vector register), the value written into aic_svr corresponding to the current interrupt is returned. this feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as aic_ivr is mapped at the absolute address 0xffff f100 and thus accessible from the arm interrupt vector at address 0x0000 0018 through the following instruction: ldr pc,[pc,# -&f20] when the processor executes this instruction, it loads the read value in aic_ivr in its program counter, thus branching the execution on the correct interrupt handler. this feature is often not used when the application is based on an operating system (either real time or not). operating systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the interrupt. however, it is strongly recommended to port the operating system on at91 products by sup- porting the interrupt vectoring. this can be performed by defining all the aic_svr of the interrupt source to be handled by the operating system at the address of its interrupt handler. when doing so, the interrupt vectoring permits a critical interrupt to transfer the execution on a specific very fast handler and not onto the operating system?s general interrupt handler. this facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral handling) to be handled efficiently and independently of the application running under an operating system. interrupt handlers this section gives an overview of the fast interrupt handling sequence when using the aic. it is assumed that the programmer understands the architecture of the arm processor, and especially the processor interrupt modes and the associated status bits. it is assumed that: 1. the advanced interrupt controller has been programmed, aic_svr registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled. 2. the instruction at the arm interrupt exception vector address is required to work with the vectoring ldr pc, [pc, # -&f20] when nirq is asserted, if the bit ?i? of cpsr is 0, the sequence is as follows: 1. the cpsr is stored in spsr_irq, the current value of the program c ounter is loaded in the interrupt link register (r14_irq) and th e program counter (r15) is loaded with
139 at91sam7s64 preliminary 6070a?atarm?28-oct-04 0x18. in the following cycle during fetch at address 0x1c, the arm core adjusts r14_irq, decrementing it by four. 2. the arm core enters interrupt mode, if it has not already done so. 3. when the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in aic_ivr. reading the aic_ivr has the following effects: ? sets the current interrupt to be the pending and enabled interrupt with the highest priority. the current level is the priority level of the current interrupt. ? de-asserts the nirq line on the processor. even if vectoring is not used, aic_ivr must be read in order to de-assert nirq. ? automatically clears the interrupt, if it has been programmed to be edge-triggered. ? pushes the current level and the current interrupt number on to the stack. ? returns the value written in the aic_svr corresponding to the current interrupt. 4. the previous step has the effect of branching to the corresponding interrupt service routine. this should start by saving the link register (r14_irq) and spsr_irq. the link register must be decremented by four when it is saved if it is to be restored directly into the program counter at the end of the interrupt. for example, the instruction sub pc, lr, #4 may be used. 5. further interrupts can then be unmasked by clearing the ?i? bit in cpsr, allowing re- assertion of the nirq to be taken into account by the core. this can happen if an inter- rupt with a higher priority than the current interrupt occurs. 6. the interrupt handler can then proceed as required, saving the registers that will be used and restoring them at the end. during this phase, an interrupt of higher priority than the current level will rest art the sequence from step 1. note: if the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase. 7. the ?i? bit in cpsr must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. the end of interrupt command register (aic_eoicr) must be written in order to indi- cate to the aic that the current interrupt is finished. this causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. if another interrupt is pending, with lower or equal priority than the old current level but with higher priority than the new current level, the nirq line is re-asserted, but the interrupt sequence does not immediately start because the ?i? bit is set in the core. spsr_irq is restored. finally, the saved value of the link register is restored directly into the pc. this has the effect of returning from the interrupt to whatever was being executed before, and of loading the cpsr with the stored spsr, masking or unmask- ing the interrupts depending on the state saved in spsr_irq. note: the ?i? bit in spsr is significant. if it is set, it indicates that the arm core was on the verge of masking an interrupt when the mask instruction was interrupted. hence, when spsr is restored, the mask instruction is completed (interrupt is masked). fast interrupt fast interrupt source the interrupt source 0 is the only source which can raise a fast interrupt request to the proces- sor except if fast forcing is used. the interrupt source 0 is generally connected to a fiq pin of the product, either directly or through a pio controller. fast interrupt control the fast interrupt logic of the aic has no priority controller. the mode of interrupt source 0 is programmed with the aic_smr0 and the field prior of this register is not used even if it reads what has been written. the field srctype of aic_smr0 enables programming the
140 at91sam7s64 preliminary 6070a?atarm?28-oct-04 fast interrupt source to be positive-edge tr iggered or negative-edge triggered or high-level sen- sitive or low-level sensitive writing 0x1 in the aic_iecr (interrupt enable command register) and aic_idcr (interrupt disable command register) respectively enables and disables the fast interrupt. the bit 0 of aic_imr (interrupt mask register) indicates whether the fast interrupt is enabled or disabled. fast interrupt vectoring the fast interrupt handler address can be stored in aic_svr0 (source vector register 0). the value written into this register is returned when the processor reads aic_fvr (fast vec- tor register). this offers a way to branch in one single instruction to the interrupt handler, as aic_fvr is mapped at the absolute address 0xffff f104 and thus accessible from the arm fast interrupt vector at address 0x0000 001c through the following instruction: ldr pc,[pc,# -&f20] when the processor executes this instruction it loads the value read in aic_fvr in its pro- gram counter, thus branching the execution on the fast interrupt handler. it also automatically performs the clear of the fast interrupt source if it is programmed in edge-triggered mode. fast interrupt handlers this section gives an overview of the fast interrupt handling sequence when using the aic. it is assumed that the programmer understands the architecture of the arm processor, and especially the processor interrupt modes and associated status bits. assuming that: 1. the advanced interrupt controller has been programmed, aic_svr0 is loaded with the fast interrupt service routine address, and the interrupt source 0 is enabled. 2. the instruction at address 0x1c (fiq exception vector address) is required to vector the fast interrupt: ldr pc, [pc, # -&f20] 3. the user does not need nested fast interrupts. when nfiq is asserted, if the bit "f" of cpsr is 0, the sequence is: 1. the cpsr is stored in spsr_fiq, the current value of the program c ounter is loaded in the fiq link register (r14_fiq) and the program counter (r15) is loaded with 0x1c. in the following cycle, during fetch at address 0x20, the arm core adjusts r14_fiq, decre- menting it by four. 2. the arm core enters fiq mode. 3. when the instruction loaded at address 0x1c is executed, the program counter is loaded with the value read in aic_fvr. reading the aic_fvr has effect of automati- cally clearing the fast interrupt, if it has been programmed to be edge triggered. in this case only, it de-asserts the nfiq line on the processor. 4. the previous step enables branching to the corresponding interrupt service routine. it is not necessary to save the link register r14_fiq and spsr_fiq if nested fast interrupts are not needed. 5. the interrupt handler can then proceed as required. it is not necessary to save regis- ters r8 to r13 because fiq mode has its own dedicated registers and the user r8 to r13 are banked. the other registers, r0 to r7, must be saved before being used, and restored at the end (before the next step). note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the interrupt source 0. 6. finally, the link register r14_fiq is restored into the pc after decrementing it by four (with instruction sub pc, lr, #4 for example). this has the effect of returning from the interrupt to whatever was being executed before, loading the cpsr with the spsr
141 at91sam7s64 preliminary 6070a?atarm?28-oct-04 and masking or unmasking the fast interrupt depending on the state saved in the spsr. note: the "f" bit in spsr is significant. if it is set, it indicates that the arm core was just about to mask fiq interrupts when the mask instruction was interrupted. hence when the spsr is restored, the interrupted instruction is completed (fiq is masked). another way to handle the fast interrupt is to map the interrupt service routine at the address of the arm vector 0x1c. this method does not use the vectoring, so that reading aic_fvr must be performed at the very beginning of the handler operation. however, this method saves the execution of a branch instruction. fast forcing the fast forcing feature of the advanced interrupt controller provides redirection of any nor- mal interrupt source on the fast interrupt controller. fast forcing is enabled or disabled by writing to the fast forcing enable register (aic_ffer) and the fast forcing disable register (aic_ffdr). writing to these registers results in an update of the fast forcing status register (aic_ffsr) that controls the feature for each internal or external interrupt source. when fast forcing is disabled, the interrupt sources are handled as described in the previous pages. when fast forcing is enabled, the edge/level programming and, in certain cases, edge detec- tion of the interrupt source is still active but the source cannot trigger a normal interrupt to the processor and is not seen by the priority handler. if the interrupt source is programmed in level-sensitive mode and an active level is sampled, fast forcing results in the assertion of the nfiq line to the core. if the interrupt source is programmed in edge-triggered mode and an active edge is detected, fast forcing results in the assertion of the nfiq line to the core. the fast forcing feature does not affect the source 0 pending bit in the interrupt pending register (aic_ipr). the fast interrupt vector register (aic_fvr) reads the contents of the source vector regis- ter 0 (aic_svr0), whatever the source of the fast interrupt may be. the read of the fvr does not clear the source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the interrupt clear command register (aic_iccr). all enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edge-triggered mode must be cleared by writing to the interrupt clear command register. in doing so, they are cleared independently and thus lost interrupts are prevented. the read of aic_ivr does not clear the source that has the fast forcing feature enabled. the source 0, reserved to the fast interrupt, continues operating normally and becomes one of the fast interrupt sources.
142 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 52. fast forcing protect mode the protect mode permits reading the interrupt vector register without performing the associ- ated automatic operations. this is necessary when working with a debug system. when a debugger, working either with a debug monitor or the arm processor's ice, stops the applica- tions and updates the opened windows, it might read the aic user interface and thus the ivr. this has undesirable consequences: if an enabled interrupt with a higher priority than the current one is pending, it is stacked. if there is no enabled pending interrupt, the spurious vector is returned. in either case, an end of interrupt command is necessary to acknowledge and to restore the context of the aic. this operation is generally not performed by the debug system as the debug system would become strongly intrusive and cause the application to enter an undes- ired state. this is avoided by using the protect mode. writing dbgm in aic_dcr (debug control regis- ter) at 0x1 enables the protect mode. when the protect mode is enabled, the aic performs interrupt stacking only when a write access is performed on the aic_ivr. therefore, the interrupt service routines must write (arbitrary data) to the aic_ivr just after reading it. the new context of the aic, including the value of the interrupt status register (aic_isr), is updated with the current interrupt only when aic_ivr is written. an aic_ivr read on its own (e.g., by a debugger), modifies neither the aic context nor the aic_isr. extra aic_ivr reads perform the same operations. however, it is recommended to not stop the processor between the read and the write of aic_ivr of the interrupt service rou- tine to make sure the debugger does not modify the aic context. to summarize, in normal operating mode, the read of aic_ivr performs the following opera- tions within the aic: 1. calculates active interrupt (higher than current or spurious). 2. determines and returns the vector of the active interrupt. 3. memorizes the interrupt. 4. pushes the current priority level onto the internal stack. 5. acknowledges the interrupt. however, while the protect mode is activated, only operations 1 to 3 are performed when aic_ivr is read. operations 4 and 5 are only performed by the aic when aic_ivr is written. source 0 _ fiq input stage automatic clear input stage automatic clear source n aic_ipr aic_imr aic_ffsr aic_ipr aic_imr priority manager nfiq nirq read ivr if source n is the current interrupt and if fast forcing is disabled on source n. read fvr if fast forcing is disabled on sources 1 to 31.
143 at91sam7s64 preliminary 6070a?atarm?28-oct-04 software that has been written and debugged using the protect mode runs correctly in normal mode without modification. however, in normal mode the aic_ivr write has no effect and can be removed to optimize the code. spurious interrupt the advanced interrupt controller features protection against spurious interrupts. a spurious interrupt is defined as being the assertion of an interrupt source long enough for the aic to assert the nirq, but no longer present when aic_ivr is read. this is most prone to occur when: an external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time. an internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (as in the case for the watchdog.) an interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source. the aic detects a spurious interrupt at the time the aic_ivr is read while no enabled interrupt source is pending. when this happens, the aic returns the value stored by the programmer in aic_spu (spurious vector register). the programmer must store the address of a spurious interrupt handler in aic_spu as part of the application, to enable an as fast as possible return to the normal execution flow. this handler writes in aic_eoicr and performs a return from interrupt. general interrupt mask the aic features a general interrupt mask bit to prevent interrupts from reaching the proces- sor. both the nirq and the nfiq lines are driven to their inactive state if the bit gmsk in aic_dcr (debug control register) is set. however, this mask does not prevent waking up the processor if it has entered idle mode. this function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt. it is strongly recommended to use this mask with caution.
144 at91sam7s64 preliminary 6070a?atarm?28-oct-04 advanced interrupt controller (aic) user interface base address the aic is mapped at the address 0xffff f000 . it has a total 4-kbyte addressing space. this permits the vectoring feature, as the pc-relative load/store instructions of the arm processor support only an 4-kbyte offset. note: 1. the reset value of this register depends on the level of the external interrupt source. all other sources are cleared at reset, thus not pending. table 46. advanced interrupt controller (aic) register mapping offset register name access reset value 0000 source mode register 0 aic_smr0 read/write 0x0 0x04 source mode register 1 aic_smr1 read/write 0x0 --- --- --- --- --- 0x7c source mode register 31 aic_smr31 read/write 0x0 0x80 source vector register 0 aic_svr0 read/write 0x0 0x84 source vector register 1 aic_svr1 read/write 0x0 --- --- --- --- --- 0xfc source vector register 31 aic_svr31 read/write 0x0 0x100 interrupt vector register aic_ivr read-only 0x0 0x104 fast interrupt vector register aic_fvr read-only 0x0 0x108 interrupt status register aic_isr read-only 0x0 0x10c interrupt pending register aic_ipr read-only 0x0 (1) 0x110 interrupt mask register aic_imr read-only 0x0 0x114 core interrupt status register aic_cisr read-only 0x0 0x118 reserved --- --- --- 0x11c reserved --- --- --- 0x120 interrupt enable command register aic_iecr write-only --- 0x124 interrupt disable command register aic_idcr write-only --- 0x128 interrupt clear command register aic_iccr write-only --- 0x12c interrupt set command register aic_iscr write-only --- 0x130 end of interrupt command register aic_eoicr write-only --- 0x134 spurious interrupt vector register aic_spu read/write 0x0 0x138 debug control register aic_dcr read/write 0x0 0x13c reserved --- --- --- 0x140 fast forcing enable register aic_ffer write-only --- 0x144 fast forcing disable register aic_ffdr write-only --- 0x148 fast forcing status register aic_ffsr read-only 0x0
145 at91sam7s64 preliminary 6070a?atarm?28-oct-04 aic source mode register register name: aic_smr0..aic_smr31 access type: read/write reset value: 0x0 prior: priority level programs the priority level for all sources except fiq source (source 0). the priority level can be between 0 (lowest) and 7 (highest). the priority level is not used for the fiq in the related smr register aic_smrx. srctype: interrupt source type the active level or edge is not programmable for the internal interrupt sources. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? srctype ? ? prior srctype internal interrupt sources 0 0 level sensitive 0 1 edge triggered 1 0 level sensitive 1 1 edge triggered
146 at91sam7s64 preliminary 6070a?atarm?28-oct-04 aic source vector register register name: aic_svr0..aic_svr31 access type: read/write reset value: 0x0 vector: source vector the user may store in these registers the addresses of the corresponding handler for each interrupt source. aic interrupt vector register register name: aic_ivr access type: read-only reset value: 0 irqv: interrupt vector register the interrupt vector register contains the vector programmed by the user in the source vector register corresponding to the current interrupt. the source vector register is indexed using the current in terrupt number when the interrupt vector register is read. when there is no current interrupt, the interrupt vector register reads the value stored in aic_spu. 31 30 29 28 27 26 25 24 vector 23 22 21 20 19 18 17 16 vector 15 14 13 12 11 10 9 8 vector 76543210 vector 31 30 29 28 27 26 25 24 irqv 23 22 21 20 19 18 17 16 irqv 15 14 13 12 11 10 9 8 irqv 76543210 irqv
147 at91sam7s64 preliminary 6070a?atarm?28-oct-04 aic fiq vector register register name: aic_fvr access type: read-only reset value: 0 fiqv: fiq vector register the fiq vector register contains the vector programmed by the us er in the source vector register 0. when there is no fast interrupt, the fast interrupt vector register reads the value stored in aic_spu. 31 30 29 28 27 26 25 24 fiqv 23 22 21 20 19 18 17 16 fiqv 15 14 13 12 11 10 9 8 fiqv 76543210 fiqv
148 at91sam7s64 preliminary 6070a?atarm?28-oct-04 aic interrupt status register register name: aic_isr access type: read-only reset value: 0 irqid: current interrupt identifier the interrupt status register returns the current interrupt source number. aic interrupt pending register register name: aic_ipr access type: read-only reset value: 0 fiq, sys, pid2-pid31: interrupt pending 0 = corresponding interrupt is not pending. 1 = corresponding interrupt is pending. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??? irqid 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
149 at91sam7s64 preliminary 6070a?atarm?28-oct-04 aic interrupt mask register register name: aic_imr access type: read-only reset value: 0 fiq, sys, pid2-pid31: interrupt mask 0 = corresponding interrupt is disabled. 1 = corresponding interrupt is enabled. aic core interrupt status register register name: aic_cisr access type: read-only reset value: 0 nfiq: nfiq status 0 = nfiq line is deactivated. 1 = nfiq line is active. nirq: nirq status 0 = nirq line is deactivated. 1 = nirq line is active. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????nirqnifq
150 at91sam7s64 preliminary 6070a?atarm?28-oct-04 aic interrupt enable command register register name: aic_iecr access type: write-only fiq, sys, pid2-pid3: interrupt enable 0 = no effect. 1 = enables corresponding interrupt. aic interrupt disable command register register name: aic_idcr access type: write-only fiq, sys, pid2-pid31: interrupt disable 0 = no effect. 1 = disables corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
151 at91sam7s64 preliminary 6070a?atarm?28-oct-04 aic interrupt clear command register register name: aic_iccr access type: write-only fiq, sys, pid2-pid31: interrupt clear 0 = no effect. 1 = clears corresponding interrupt. aic interrupt set command register register name: aic_iscr access type: write-only fiq, sys, pid2-pid31: interrupt set 0 = no effect. 1 = sets corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
152 at91sam7s64 preliminary 6070a?atarm?28-oct-04 aic end of interrupt command register register name: aic_eoicr access type: write-only the end of interrupt command register is used by the interrupt routine to indicate that the interrupt treatment is complete. any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. aic spurious interrupt vector register register name: aic_spu access type: read/write reset value: 0 siqv: spurious interrupt vector register the user may store the address of a spurious interrupt handler in this register. the written value is returned in aic_ivr in case of a spurious interrupt and in aic_fvr in case of a spurious fast interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????? 31 30 29 28 27 26 25 24 siqv 23 22 21 20 19 18 17 16 siqv 15 14 13 12 11 10 9 8 siqv 76543210 siqv
153 at91sam7s64 preliminary 6070a?atarm?28-oct-04 aic debug control register register name: aic_debug access type: read/write reset value: 0 prot: protection mode 0 = the protection mode is disabled. 1 = the protection mode is enabled. gmsk: general mask 0 = the nirq and nfiq lines are normally controlled by the aic. 1 = the nirq and nfiq lines are tied to their inactive state. aic fast forcing enable register register name: aic_ffer access type: write-only sys, pid2-pid31: fast forcing enable 0 = no effect. 1 = enables the fast forcing feature on the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????gmskprot 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys ?
154 at91sam7s64 preliminary 6070a?atarm?28-oct-04 aic fast forcing disable register register name: aic_ffdr access type: write-only sys, pid2-pid31: fast forcing disable 0 = no effect. 1 = disables the fast forcing feature on the corresponding interrupt. aic fast forcing status register register name: aic_ffsr access type: read-only sys, pid2-pid31: fast forcing status 0 = the fast forcing feature is disabled on the corresponding interrupt. 1 = the fast forcing feature is enabled on the corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys ? 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys ?
155 at91sam7s64 preliminary 6070a?atarm?28-oct-04 clock generator description the clock generator is made up of 1 pll, a main oscillator, an rc oscillator and it provides the following clocks: slck, the slow clock, which is the only permanent clock within the system. mainck is the output of the main oscillator pllck is the output of the divider and pll block the clock generator user interface is embedded within the power management controller one and is described in ?power management controller (pmc) user interface? on page 166. however, the clock generator registers are named ckgr_. slow clock rc oscillator the slow clock is the output of the rc oscillator and is the only clock considered permanent in a system that includes the power management controller. it is mandatory in the operations of the pmc. the user has to take the possible drifts of the rc oscillator into account. more details are given in the dc characteristics section of the product datasheet. main oscillator figure 53 shows the main oscillator block diagram. figure 53. main oscillator block diagram main oscillator connections the clock generator integrates a main oscillator that is designed for a 3 to 20 mhz funda- mental crystal. the typical crystal connection is illustrated in figure 54. the 1 k ? resistor is only required for crystals with frequencies lower than 8 mhz. the oscillator contains 25 pf capacitors on each xin and xout pin. consequently, cl1 and cl2 can be removed when a crystal with a load capacitance of 12.5 pf is used. for further details on the electrical charac- teristics of the main oscillator, see the dc characteristics section of the product datasheet. main oscillator xin xout moscen main oscillator counter oscount moscs mainck main clock main clock frequency counter mainf mainrdy slck slow clock
156 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 54. typical crystal connection main oscillator startup time the startup time of the main oscillator is given in the dc characteristics section of the product datasheet. the startup time depends on the crystal frequency and decreases when the fre- quency rises. main oscillator control to minimize the power required to start up the system, the main oscillator is disabled after reset and slow clock is selected. the software enables or disables the main oscillator so as to reduce power consumption by clearing the moscen bit in the main oscillator register (ckgr_mor). when disabling the main oscillator by clearing the moscen bit in ckgr_mor, the moscs bit in pmc_sr is automatically cleared, indicating the main clock is off. when enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to the startup time of t he oscillator. this star tup time depends on the crystal frequency connected to the main oscillator. when the moscen bit and the oscount are written in ckgr_mor to enable the main oscillator, the moscs bit in pmc_sr (status register) is cleared and the counter starts counting down on the slow clock divided by 8 from the oscount value. since the oscount value is coded with 8 bits, the maximum startup time is about 62 ms. when the counter reaches 0, the moscs bit is set, indicating that the main clock is valid. set- ting the moscs bit in pmc_imr can trigger an interrupt to the processor. main clock frequency counter the main oscillator f eatures a main clock frequency counter that provides the quartz fre- quency connected to the main oscillator. generally, this value is known by the system designer; however, it is useful for the boot program to configure the device with the correct clock speed, independently of the application. the main clock frequency counter starts incrementing at the main clock speed after the next rising edge of the slow clock as soon as the ma in oscillator is stable, i.e., as soon as the moscs bit is set. then, at the 16th falling edge of slow clock, the mainrdy bit in ckgr_mcfr (main clock frequency register) is set and the counter stops counting. its value can be read in the mainf field of ckgr_mcfr and gives the number of main clock cycles during 16 periods of slow clock, so that the frequency of the crystal connected on the main oscillator can be determined. main oscillator bypass the user can input a clock on the device instead of connecting a crystal. in this case, the user has to provide the external clock signal on the xin pin. the input characteristics of the xin pin under these conditions are given in the product electrical characteristics section. the program- mer has to be sure to set the oscbypass bit to 1 and the moscen bit to 0 in the main osc register (ckgr_mor) for the external clock to operate properly. 1k xin xout gnd c l2 c l1
157 at91sam7s64 preliminary 6070a?atarm?28-oct-04 divider and pll block the pll embeds an input divider to increase the accuracy of the resulting clock signals. how- ever, the user must respect the pll minimum input frequency when programming the divider. figure 55 shows the block diagram of the divider and pll block. figure 55. divider and pll block diagram pll filter the pll requires connection to an external second-order filter through the pllrc pin. figure 56 shows a schematic of these filters. figure 56. pll capacitors and resistors values of r, c1 and c2 to be connected to the pllrc pin must be calculated as a function of the pll input frequency, the pll output frequency and the phase margin. a trade-off has to be found between output signal overshoot and startup time. divider and phase lock loop programming the divider can be set between 1 and 255 in steps of 1. when a divider field (div) is set to 0, the output of the corresponding divider and the pll output is a continuous signal at level 0. on reset, each div field is set to 0, thus the corresponding pll input clock is set to 0. the pll allows multiplication of the divider?s outputs. the pll clock signal has a frequency that depends on the respective source signal frequency and on the parameters div and mul. the factor applied to the source signal frequency is (mul + 1)/div. when mul is written to 0, the corresponding pll is disabled and its power consumption is saved. re-enabling the pll can be performed by writing a value higher than 0 in the mul field. whenever the pll is re-enabled or one of its parameters is changed, the lock bit in pmc_sr is automatically cleared. the values written in the pllcount field in ckgr_pllr are loaded in the pll counter. the pll counter then decrements at the speed of the slow clock until it reaches 0. at this time, the lock bit is set in pmc_sr and can trigger an inter- rupt to the processor. the user has to load the number of slow clock cycles required to cover the pll transient time into the pllcount field. the transient time depends on the pll filter. the initial state of the pll and its target frequency can be calculated using a specific tool pro- vided by atmel. divider pllrc div pll mul pll counter pllcount lock out slck mainck pllck gnd c1 c2 pll pllrc r
158 at91sam7s64 preliminary 6070a?atarm?28-oct-04 power management controller (pmc) description the power management controller (pmc) optimiz es power consumpti on by controlling all system and user peripheral clocks. the pmc enables/disables the clock inputs to many of the peripherals and the arm processor. the power management controller provides the following clocks: mck, the master clock, programmable from a few hundred hz to the maximum operating frequency of the device. it is available to the modules running permanently, such as the aic and the memory controller. processor clock (pck), switched off when entering processor in idle mode. peripheral clocks, typically mck, provided to the embedded peripherals (usart, ssc, spi, twi, tc, mci, etc.) and independently controllable. in order to reduce the number of clock names in a product, the peripheral clocks are named mck in the product datasheet. udp clock (udpck), required by usb device port operations. programmable clock outputs can be selected from the clocks provided by the clock generator and driven on the pckx pins. master clock controller the master clock controller provides selection and division of the master clock (mck). mck is the clock provided to all the peripherals and the memory controller. the master clock is selected from one of the clocks provided by the clock generator. select- ing the slow clock provides a slow clock signal to the whole device. selecting the main clock saves power consumption of the pll. the master clock controller is made up of a clock selector and a prescaler. the master clock selection is made by writing the css field (clock source selection) in pmc_mckr (master clock register). the prescaler supports the division by a power of 2 of the selected clock between 1 and 64. the pres field in pmc_mckr programs the prescaler. each time pmc_mckr is written to define a new master clock, the mckrdy bit is cleared in pmc_sr. it reads 0 until the master clock is established. then, the mckrdy bit is set and can trigger an interrupt to the processor. this feature is useful when switching from a high- speed clock to a lower one to inform the software when the change is actually done. figure 57. master clock controller processor clock controller the pmc features a processor clock controller (pck) that implements the processor idle mode. the processor clock can be enabled and disabled by writing the system clock enable (pmc_scer) and system clock disable registers (pmc_scdr). the status of this clock (at least for debug purpose) can be read in the system clock status register (pmc_scsr). slck master clock prescaler mck pres css mainck pllck to the processor clock controller (pck) pmc_mckr pmc_mckr
159 at91sam7s64 preliminary 6070a?atarm?28-oct-04 the processor clock pck is enabled after a reset and is automatically re-enabled by any enabled interrupt. the processor idle mode is achieved by disabling the processor clock, which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product. when the processor clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus. usb clock controller the usb source clock is the pll output. if using the usb, the user must program the pll to generate a 48 mhz, a 96 mhz or a 192 mhz signal with an accuracy of 0.25% depending on the usbdiv bit in ckgr_pllr. when the pll output is stable, i.e., the lock bit is set: the usb device clock can be enabled by setting the udp bit in pmc_scer. to save power on this peripheral when it is not used, the user can set the udp bit in pmc_scdr. the udp bit in pmc_scsr gives the activity of this clock. the usb device port require both the 48 mhz signal and the master clock. the master clock may be controlled via the peripheral clock controller. figure 58. usb clock controller peripheral clock controller the power management controller controls the clocks of each embedded peripheral by the way of the peripheral clock controller. the user can individually enable and disable the mas- ter clock on the peripherals by writing into the peripheral clock enable (pmc_pcer) and peripheral clock disable (pmc_pcdr) registers. the status of the peripheral clock activity can be read in the peripheral clock status register (pmc_pcsr). when a peripheral clock is disabled, the clock is immediately stopped. the peripheral clocks are automatically disabled after a reset. in order to stop a peripheral, it is recommended that the system software wait until the periph- eral has executed its last programmed operation before disabling the clock. this is to avoid data corruption or erroneous behavior of the system. the bit number within the peripheral clock control registers (pmc _pcer, pmc_pcdr, and pmc_pcsr) is the peripheral identifier defined at the product level. generally, the bit number corresponds to the interrupt source number assigned to the peripheral. programmable clock output controller the pmc controls 3 signals to be output on external pins pckx. each signal can be indepen- dently programmed via the pmc_pckx registers. pckx can be independently selected between the slow clock, the pll output and the main clock by writing the css field in pmc_pckx. each output signal can also be divided by a power of 2 between 1 and 64 by writing the pres (prescaler) field in pmc_pckx. each output signal can be enabled and disabled by writing 1 in the corresponding bit, pckx of pmc_scer and pmc_scdr, respectively. status of the active programmable output clocks are given in the pckx bits of pmc_scsr (system clock status register). usb source clock udp clock (udpck) udp usbdiv divider /1,/2,/4
160 at91sam7s64 preliminary 6070a?atarm?28-oct-04 moreover, like the pck, a status bit in pmc_sr indicates that the programmable clock is actually what has been programmed in the programmable clock registers. as the programmable clock controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the programmable clock before any configura- tion change and to re-enable it after the change is actually performed. programming sequence 1. enabling the main oscillator: the main oscillator is enabled by setting the moscen field in the ckgr_mor register. in some cases it may be advantageous to define a start-up time. this can be achieved by writing a value in the oscount field in the ckgr_mor register. once this register has been correctly configured, the user must wait for moscs field in the pmc_sr register to be set. this can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to moscs has been enabled in the pmc_ier register. code example: write_register(ckgr_mor,0x00000701) start up time = 8 * oscount / slck = 56 slow clock cycles. so, the main oscillator will be enabled (moscs bit set) after 56 slow clock cycles. 2. checking the main oscillator frequency (optional): in some situations the user may need an accurate measure of the main oscillator fre- quency. this measure can be accomplished via the ckgr_mcfr register. once the mainrdy field is set in ckgr_mcfr register, the user may read the mainf field in ckgr_mcfr register. this provides the number of main clock cycles within six- teen slow clock cycles. 3. setting pll and divider: all parameters needed to configure pll and the divider are located in the ckgr_pllr register. the div field is used to control divider itself. a value between 0 and 255 can be pro- grammed. divider output is divider input divided by div parameter. by default div parameter is set to 0 which means that divider is turned off. the out field is used to select the pll b output frequency range. the mul field is the pll multiplier factor . this parameter can be programmed between 0 and 2047. if mul is set to 0, pll will be turned off, otherwise the pll output frequency is pll input frequency multiplied by (mul + 1). the pllcount field specifies the number of slow clock cycles before lock bit is set in the pmc_sr register after ckgr_pllr register has been written. once the pmc_pll register has been written, the user must wait for the lock bit to be set in the pmc_sr register. this can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to lock has been enabled in the pmc_ier register. all parameters in ckgr_pllr can be programmed in a single write operation. if at some stage one of the following parameters, mul, div is modified, lock bit will go low to indicate that pll is not ready yet. when pll is locked, lock will be set again. the user is constrained to wait for lock bit to be set before using the pll output clock. the usbdiv field is used to control the additional divider by 1, 2 or 4, which generates the usb clock(s).
161 at91sam7s64 preliminary 6070a?atarm?28-oct-04 code example: write_register(ckgr_pllr,0x00040805) if pll and divider are enabled, the pll input clock is the main clock. pll output clock is pll input clock multiplied by 5. once ckgr _pllr has been written, lock bit will be set after eight slow clock cycles. 4. selection of master clock and processor clock the master clock and the processor clock are configurable via the pmc_mckr register. the css field is used to select the master clock divider source. by default, the selected clock source is slow clock. the pres field is used to control the master clock prescaler. the user can choose between different values (1, 2, 4, 8, 16, 32, 64). master clock output is prescaler input divided by pres parameter. by default, pres parameter is set to 1 which means that master clock is equal to slow clock. once pmc_mckr register has been written, the user must wait for the mckrdy bit to be set in the pmc_sr register. this can be done either by polling the status register or by waiting for the interrupt line to be raised if the associated interrupt to mckrdy has been enabled in the pmc_ier register. all parameters in pmc_mckr can be programmed in a single write operation. if at some stage one of the following parameters, css or pres, is modified, the mckrdy bit will go low to indicate that the master clock and the processor clock are not ready yet. the user must wait for mckrdy bit to be set again before using the master and processor clocks. note: if pllx clock was selected as the master clock and the user decides to modify it by writing in ckgr_pllr, the mckrdy flag will go low while pll is unlocked. once pll is locked again, lock goes high and mckrdy is set. while pll is unlocked, the master clock selection is automatically changed to main clock. for further information, see ?clock switching waveforms? on page 163. code example: write_register(pmc_mckr,0x00000011) the master clock is main clock divided by 16. the processor clock is the master clock. 5. selection of programmable clocks programmable clocks are controlled via registers; pmc_scer, pmc_scdr and pmc_scsr. programmable clocks can be enabled and/or disabled via the pmc_scer and pmc_scdr registers. depending on the system used, 3 programmable clocks can be enabled or disabled. the pmc_scsr provides a clear indication as to which programma- ble clock is enabled. by default all programmable clocks are disabled. pmc_pckx registers are used to configure programmable clocks. the css field is used to select the programmable clock divider source. four clock options are available: main clock, slow clock, pllck. by default, the clock source selected is slow clock. the pres field is used to control the programmable clock prescaler. it is possible to choose between different values (1, 2, 4, 8, 16, 32, 64). programmable clock output is
162 at91sam7s64 preliminary 6070a?atarm?28-oct-04 prescaler input divided by pres parameter. by default, the pres parameter is set to 1 which means that master clock is equal to slow clock. once the pmc_pckx register has been programmed, the corresponding programmable clock must be enabled and the user is constrained to wait for the pckrdyx bit to be set in the pmc_sr register. this can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to pckrdyx has been enabled in the pmc_ier register. all parameters in pmc_pckx can be programmed in a single write operation. if the css and pres parameters are to be modified, the corresponding programmable clock must be disabled first. the parameters can then be modified. once this has been done, the user must re-enable the programmable clock and wait for the pckrdyx bit to be set. code example: write_register(pmc_pck0,0x00000015) programmable clock 0 is main clock divided by 32. 6. enabling peripheral clocks once all of the previous steps have been completed, t he peripheral cl ocks can be enabled and/or disabled via registers pmc_pcer and pmc_pcdr. depending on the system used, 9 peripheral clocks can be enabled or disabled. the pmc_pcsr provides a clear view as to which peripheral clock is enabled. note: each enabled peripheral clock corresponds to master clock. code examples: write_register(pmc_pcer,0x00000110) peripheral clocks 4 and 8 are enabled. write_register(pmc_pcdr,0x00000010) peripheral clock 4 is disabled.
163 at91sam7s64 preliminary 6070a?atarm?28-oct-04 clock switching details master clock switching timings table 47 gives the worst case timing required for the master clock to switch from one selected clock to another one. this is in the event that the prescaler is de-activated. when the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. clock switching waveforms figure 59. switch master clock from slow clock to pll clock table 47. clock switching timings (worst case) from main clock slck pll clock to main clock ? 4 x slck + 2.5 x main clock 3 x pll clock + 4 x slck + 1 x main clock slck 0.5 x main clock + 4.5 x slck ? 3 x pll clock + 5 x slck pll clock 0.5 x main clock + 4 x slck + pllcount x slck + 2.5 x pllx clock 2.5 x pll clock + 5 x slck + pllcount x slck 2.5 x pll clock + 4 x slck + pllcount x slck slow clock lock mckrdy master clock write pmc_mckr pll clock
164 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 60. switch master clock from main clock to slow clock figure 61. change pll programming slow clock main clock mckrdy master clock write pmc_mckr slow clock slow clock pll clock lock mckrdy master clock write ckgr_pllr
165 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 62. programmable clock output programming pll clock pckrdy pckx output write pmc_pckx write pmc_scer write pmc_scdr pckx is disabled pckx is enabled pll clock is selected
166 at91sam7s64 preliminary 6070a?atarm?28-oct-04 power management controller (pmc) user interface table 48. power management controller (pmc) register mapping offset register name access reset value 0x0000 system clock enable register pmc_scer write-only ? 0x0004 system clock disable register pmc_scdr write-only ? 0x0008 system clock status register pmc _scsr read-only 0x01 0x000c reserved ? ? ? 0x0010 peripheral clock enable register pmc _pcer write-only ? 0x0014 peripheral clock disable register pmc_pcdr write-only ? 0x0018 peripheral clock status register pmc_pcsr read-only 0x0 0x001c reserved ? ? ? 0x0020 main oscillator register ckgr_mor read/write 0x0 0x0024 main clock frequency register ckgr_mcfr read-only - 0x0028 reserved ? ? ? 0x002c pll register ckgr_pllr read/write 0x3f00 0x0030 master clock register pmc_mckr read/write 0x0 0x0038 reserved ? ? ? 0x003c reserved ? ? ? 0x0040 programmable clock 0 register pmc_pck0 read/write 0x0 0x0044 programmable clock 1 register pmc_pck1 read/write 0x0 ... ... ... ... ... 0x0060 interrupt enable register pmc_ier write-only -- 0x0064 interrupt disable register pmc_idr write-only -- 0x0068 status register pmc_sr read-only 0x18 0x006c interrupt mask register pmc_imr read-only 0x0 0x0070 - 0x00fc reserved ? ? ?
167 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pmc system clock enable register register name: pmc_scer access type: write-only pck: processor clock enable 0 = no effect. 1 = enables the processor clock. udp: usb device port clock enable 0 = no effect. 1 = enables the 48 mhz clock of the usb device port. pckx: programmable clock x output enable 0 = no effect. 1 = enables the corresponding programmable clock output. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????pck2pck1pck0 76543210 udp??????pck
168 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pmc system clock disable register register name: pmc_scdr access type: write-only pck: processor clock disable 0 = no effect. 1 = disables the processor clock. this is used to enter the processor in idle mode. udp: usb device po rt clock disable 0 = no effect. 1 = disables the 48 mhz clock of the usb device port. pckx: programmable clock x output disable 0 = no effect. 1 = disables the corresponding programmable clock output. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????pck2pck1pck0 76543210 udp??????pck
169 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pmc system clock status register register name: pmc_scsr access type: read-only pck: processor clock status 0 = the processor clock is disabled.? 1 = the processor clock is enabled. udp: usb device port clock status 0 = the 48 mhz clock (udpck) of the usb device port is disabled. 1 = the 48 mhz clock (udpck) of the usb device port is enabled. pckx: programmable clock x output status 0 = the corresponding programmable clock output is disabled. 1 = the corresponding programmable clock output is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????pck2pck1pck0 76543210 udp??????pck
170 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pmc peripheral clock enable register register name: pmc_pcer access type: write-only pidx: peripheral clock x enable 0 = no effect. 1 = enables the corresponding peripheral clock. note: programming the control bits of the peripheral id that are not implemented has no effect on the behavior of the pmc. pmc peripheral clock disable register register name: pmc_pcdr access type: write-only pidx: peripheral clock x disable 0 = no effect. 1 = disables the corresponding peripheral clock. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 ? ? 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 ? ?
171 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pmc peripheral clock status register register name: pmc_pcsr access type: read-only pidx: peripheral clock x status 0 = the corresponding peripheral clock is disabled. 1 = the corresponding peripheral clock is enabled. pmc clock generator main oscillator register register name: ckgr_mor access type: read/write moscen: main oscillator enable a crystal must be connected between xin and xout. 0 = the main oscillator is disabled. 1 = the main oscillator is enabled. oscbypass must be set to 0. oscbypass: oscillator bypass 0 = no effect. 1 = the main oscillator is bypassed. moscen must be set to 0. an external clock must be connected on xin. oscount: main oscillator start-up time specifies the number of slow clock cycles multiplied by 8 for the main oscillator start-up time. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 ? ? 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 oscount 76543210 ??????oscbypassmoscen
172 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pmc clock generator main clock frequency register register name: ckgr_mcfr access type: read-only mainf: main clock frequency gives the number of main clock cycles within 16 slow clock periods. mainrdy: main clock ready 0 = mainf value is not valid or the main oscillator is disabled. 1 = the main oscillator has been enabled previously and mainf value is available. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????mainrdy 15 14 13 12 11 10 9 8 mainf 76543210 mainf
173 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pmc clock generator pll register register name: ckgr_pllr access type: read/write possible limitations on pll input frequencies and multiplier factors should be checked before using the pmc. div: divider pllcount: pll counter specifies the number of slow clock cycles before the lock bit is set in pmc_sr after ckgr_pllr is written. out: pll clock frequency range mul: pll multiplier 0 = the pll is deactivated. 1 up to 2047 = the pll clock frequency is the pll input frequency multiplied by mul+ 1. usbdiv: divider for usb clock 31 30 29 28 27 26 25 24 ? ? usbdiv ? mul 23 22 21 20 19 18 17 16 mul 15 14 13 12 11 10 9 8 out pllcount 76543210 div div divider selected 0 divider output is 0 1 divider is bypassed 2 - 255 divider output is the selected clock divided by div. out pll clock frequency range 00 refer to the dc characteristics section of the product datasheet 01reserved 10 refer to the dc characteristics section of the product datasheet 11reserved usbdiv divider for usb clock(s) 0 0 divider output is pll clock output. 0 1 divider output is pll clock output divided by 2. 1 0 divider output is pll clock output divided by 4. 1 1 reserved.
174 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pmc master clock register register name: pmc_mckr access type: read/write css: master clock selection pres: master clock prescaler 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? pres css css clock source selection 0 0 slow clock is selected 0 1 main clock is selected 10reserved 1 1 pll clock is selected. pres master clock 0 0 0 selected clock 0 0 1 selected clock divided by 2 0 1 0 selected clock divided by 4 0 1 1 selected clock divided by 8 1 0 0 selected clock divided by 16 1 0 1 selected clock divided by 32 1 1 0 selected clock divided by 64 1 1 1 reserved
175 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pmc programmable clock register register name: pmc_pckx access type: read/write css: master clock selection pres: programmable clock prescaler 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? pres css css clock source selection 0 0 slow clock is selected 0 1 main clock is selected 10reserved 1 1 pll clock is selected pres master clock 0 0 0 selected clock 0 0 1 selected clock divided by 2 0 1 0 selected clock divided by 4 0 1 1 selected clock divided by 8 1 0 0 selected clock divided by 16 1 0 1 selected clock divided by 32 1 1 0 selected clock divided by 64 1 1 1 reserved
176 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pmc interrupt enable register register name: pmc_ier access type: write-only moscs: main oscillator status interrupt enable lock: pll lock interrupt enable mckrdy: master clock ready interrupt enable pckrdyx: programmable clock ready x interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. pmc interrupt disable register register name: pmc_idr access type: write-only moscs: main oscillator status interrupt disable lock: pll lock interrupt disable mckrdy: master clock ready interrupt disable pckrdyx: programmable clock ready x interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????pckrdy2pckrdy1pckrdy0 76543210 ??? ? mckrdy lock ? moscs 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????pckrdy2pckrdy1pckrdy0 76543210 ??? ? mckrdy lock ? moscs
177 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pmc status register register name: pmc_sr access type: read-only moscs: moscs flag status 0 = main oscillator is not stabilized. 1 = main oscillator is stabilized. lock: pll lock status 0 = pll is not locked 1 = pll is locked. mckrdy: master clock status 0 = master clock is not ready. 1 = master clock is ready. pckrdyx: programmable clock ready status 0 = programmable clock x is not ready. 1 = programmable clock x is ready. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????pckrdy2pckrdy1pckrdy0 76543210 ??? ? mckrdy lock ? moscs
178 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pmc interrupt mask register register name: pmc_imr access type: read-only moscs: main oscillator status interrupt mask lock: pll lock interrupt mask mckrdy: master clock ready interrupt mask pckrdyx: programmable clock ready x interrupt mask 0 = the corresponding interrupt is enabled. 1 = the corresponding interrupt is disabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????pckrdy2pckrdy1pckrdy0 76543210 ??? ? mckrdy lock ? moscs
179 at91sam7s64 preliminary 6070a?atarm?28-oct-04 debug unit (dbgu) overview the debug unit provides a single entry point from the processor for access to all the debug capabilities of atmel?s arm-based systems. the debug unit features a two-pin uart that can be used for several debug and trace pur- poses and offers an ideal medium for in-situ programming solutions and debug monitor communications. moreover, the association with two peripheral data controller channels per- mits packet handling for these tasks with processor time reduced to a minimum. the debug unit also makes the debug communication channel (dcc) signals provided by the in-circuit emulator of the arm processor visible to the software. these signals indicate the status of the dcc read and write registers and generate an interrupt to the arm processor, making possible the handling of the dcc under interrupt control. chip identifier registers permit recognition of the device and its revision. these registers inform as to the sizes and types of the on-chip memories, as well as the set of embedded peripherals. finally, the debug unit features a force ntrst capability that enables the software to decide whether to prevent access to the system via the in-circuit emulator. this permits protection of the code, stored in rom.
180 at91sam7s64 preliminary 6070a?atarm?28-oct-04 block diagram figure 63. debug unit functional block diagram figure 64. debug unit application example peripheral data controller baud rate generator dcc handler ice access handler transmit receive chip id interrupt control peripheral bridge parallel input/ output dtxd drxd power management controller arm processor force_ntrst commrx commtx mck ntrst ice_nreset dbgu_irq apb debug unit table 49. debug unit pin description pin name description type drxd debug receive data input dtxd debug transmit data output debug unit rs232 drivers programming tool trace console debug console boot program debug monitor trace manager
181 at91sam7s64 preliminary 6070a?atarm?28-oct-04 product dependencies i/o lines depending on product integration, the debug unit pins may be multiplexed with pio lines. in this case, the programmer must first configure the corresponding pio controller to enable i/o lines operations of the debug unit. power management depending on product integration, the debug unit clock may be controllable through the power management controller. in this case, the programmer must first configure the pmc to enable the debug unit clock. usually, the peripheral identifier used for this purpose is 1. interrupt source depending on product integration, the debug unit interrupt line is connected to one of the interrupt sources of the advanced interrupt controller. interrupt handling requires program- ming of the aic before configuring the debug unit. usually, the debug unit interrupt line connects to the interrupt source 1 of the aic, which may be shared with the real-time clock, the system timer interrupt lines and other system peripheral interrupts, as shown in figure 63. this sharing requires the programmer to determine the source of the interrupt when the source 1 is triggered. uart operations the debug unit operates as a uart, (asynchronous mode only) and supports only 8-bit char- acter handling (with parity). it has no clock pin. the debug unit's uart is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. receiver timeout and transmitter time guard are not implemented. however, all the implemented features are compatible with those of a standard usart. baud rate generator the baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter. the baud rate clock is the master clock divided by 16 times the value (cd) written in dbgu_brgr (baud rate generator register). if dbgu_brgr is set to 0, the baud rate clock is disabled and the debug unit's uart remains inactive. the maximum allowable baud rate is master clock divided by 16. the minimum allowable baud rate is master clock divided by (16 x 65536). figure 65. baud rate generator baud rate mck 16 cd --------------------- = mck 16-bit counter 0 baud rate clock cd cd out divide by 16 0 1 >1 receiver sampling clock
182 at91sam7s64 preliminary 6070a?atarm?28-oct-04 receiver receiver reset, enable and disable after device reset, the debug unit receiver is disabled and must be enabled before being used. the receiver can be enabled by writing the control register dbgu_cr with the bit rxen at 1. at this command, the receiver starts looking for a start bit. the programmer can disable the receiver by writing dbgu_cr with the bit rxdis at 1. if the receiver is waiting for a start bit, it is immediately stopped. however, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. the programmer can also put the receiver in its reset state by writing dbgu_cr with the bit rstrx at 1. in doing so, the receiver immediately stops its current operations and is disabled, whatever its current state. if rstrx is applied when data is being processed, this data is lost. start detection and data sampling the debug unit only supports asynchronous operations, and this affects only its receiver. the debug unit receiver detects the start of a received character by sampling the drxd signal until it detects a valid start bit. a low level (space) on drxd is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. a space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. when a valid start bit has been detected, the receiver samples the drxd at the theoretical midpoint of each bit. it is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. the first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. figure 66. start bit detection figure 67. character reception receiver ready when a complete character is received, it is transferred to the dbgu_rhr and the rxrdy status bit in dbgu_sr (status register) is set. the bit rxrdy is automatically cleared when the receive holding register dbgu_rhr is read. sampling clock drxd true start detection d0 baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 drxd true start detection sampling parity bit stop bit example: 8-bit, parity enabled 1 stop 1 bit period 0.5 bit period
183 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 68. receiver ready receiver overrun if dbgu_rhr has not been read by the software (or the peripheral data controller) since the last transfer, the rxrdy bit is still set and a new character is received, the ovre status bit in dbgu_sr is set. ovre is cleared when the software writes the control register dbgu_cr with the bit rststa (reset status) at 1. figure 69. receiver overrun parity error each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field par in dbgu_mr. it then compares the result with the received parity bit. if different, the parity error bit pare in dbgu_sr is set at the same time the rxrdy is set. the parity bit is cleared when the control register dbgu_cr is written with the bit rststa (reset status) at 1. if a new character is received before the reset status com- mand is written, the pare bit remains at 1. figure 70. parity error receiver framing error when a start bit is detected, it generates a character reception when all the data bits have been sampled. the stop bit is also sampled and when it is detected at 0, the frame (framing error) bit in dbgu_sr is set at the same time the rxrdy bit is set. the bit frame remains high until the control register dbgu_cr is written with the bit rststa at 1. figure 71. receiver framing error d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p drxd read dbgu_rhr rxrdy d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p drxd rststa rxrdy ovre stop stop stop d0 d1 d2 d3 d4 d5 d6 d7 p s drxd rststa rxrdy pare wrong parity bit d0 d1 d2 d3 d4 d5 d6 d7 p s drxd rststa rxrdy frame stop bit detected at 0 stop
184 at91sam7s64 preliminary 6070a?atarm?28-oct-04 transmitter transmitter reset, enable and disable after device reset, the debug unit transmitter is disabled and it must be enabled before being used. the transmitter is enabled by writing the control register dbgu_cr with the bit txen at 1. from this command, the transmitter waits for a character to be written in the transmit hold- ing register dbgu_thr before actually starting the transmission. the programmer can disable the transmitter by writing dbgu_cr with the bit txdis at 1. if the transmitter is not operating, it is immediately stopped. however, if a character is being pro- cessed into the shift register and/or a character has been written in the transmit holding register, the characters are completed before the transmitter is actually stopped. the programmer can also put the transmitter in its reset state by writing the dbgu_cr with the bit rsttx at 1. this immediately stops the transmitter, whether or not it is processing characters. transmit format the debug unit transmitter drives the pin dtxd at the baud rate clock speed. the line is driven depending on the format defined in the mode register and the data stored in the shift register. one start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown on the following figure. the field pare in the mode register dbgu_mr defines whether or not a parity bit is shifted out. when a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. figure 72. character transmission transmitter control when the transmitter is enabled, the bit txrdy (transmitter ready) is set in the status regis- ter dbgu_sr. the transmission starts when the programmer writes in the transmit holding register dbgu_thr, and after the written character is transferred from dbgu_thr to the shift register. the bit txrdy remains high until a second character is written in dbgu_thr. as soon as the first character is completed, the last character written in dbgu_thr is trans- ferred into the shift register and txrdy rises again, showing that the holding register is empty. when both the shift register and the dbgu_thr are empty, i.e., all the characters written in dbgu_thr have been processed, the bit txempty rises after the last stop bit has been completed. d0 d1 d2 d3 d4 d5 d6 d7 dtxd start bit parity bit stop bit example: parity enabled baud rate clock
185 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 73. transmitter control peripheral data controller both the receiver and the transmitter of the debug unit's uart are generally connected to a peripheral data controller (pdc) channel. the peripheral data controller channels are programmed via registers that are mapped within the debug unit user interface from the offset 0x100. the status bits are reported in the debug unit status register dbgu_sr and can generate an interrupt. the rxrdy bit triggers the pdc channel data transfer of the receiver. this results in a read of the data in dbgu_rhr. the txrdy bit triggers the pdc channel data transfer of the trans- mitter. this results in a write of a data in dbgu_thr. test modes the debug unit supports three tests modes. these modes of operation are programmed by using the field chmode (channel mode) in the mode register dbgu_mr. the automatic echo mode allows bit-by-bit retransmission. when a bit is received on the drxd line, it is sent to the dtxd line. the transmitter operates normally, but has no effect on the dtxd line. the local loopback mode allows the transmitted characters to be received. dtxd and drxd pins are not used and the output of the transmitter is internally connected to the input of the receiver. the drxd pin level has no effect and the dtxd line is held high, as in idle state. the remote loopback mode directly connects the drxd pin to the dtxd line. the transmit- ter and the receiver are disabled and have no effect. this mode allows a bit-by-bit retransmission. dbgu_thr shift register dtxd txrdy txempty data 0 data 1 data 0 data 0 data 1 data 1 s s p p write data 0 in dbgu_thr write data 1 in dbgu_thr stop stop
186 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 74. test modes debug communication channel support the debug unit handles the signals commrx and commtx that come from the debug communication channel of the arm processor and are driven by the in-circuit emulator. the debug communication channel contains two registers that are accessible through the ice breaker on the jtag side and through the coprocessor 0 on the arm processor side. as a reminder, the following instructions are used to read and write the debug communication channel: mrc p14, 0, rd, c1, c0, 0 returns the debug communication data read register into rd mcr p14, 0, rd, c1, c0, 0 writes the value in rd to the debug communication data write register. the bits commrx and commtx, which indicate, respectively, that the read register has been written by the debugger but not yet read by t he processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of the status register dbgu_sr. these bits can generate an interrupt. this feature per- mits handling under interrupt a debug link between a debug monitor running on the target system and a debugger. receiver transmitter disabled rxd txd receiver transmitter disabled rxd txd v dd disabled receiver transmitter disabled rxd txd disabled automatic echo local loopback remote loopback v dd
187 at91sam7s64 preliminary 6070a?atarm?28-oct-04 chip identifier the debug unit features two chip identifier registers, dbgu_cidr (chip id register) and dbgu_exid (extension id). both registers contain a hard-wired value that is read-only. the first register contains the following fields: ext - shows the use of the extension identifier register nvptyp and nvpsiz - identifies the type of embedded non-volatile memory and its size arch - identifies the set of embedded peripheral sramsiz - indicates the size of the embedded sram eproc - indicates the embedded arm processor version - gives the revision of the silicon the second register is device-dependent and reads 0 if the bit ext is 0. ice access prevention the debug unit allows blockage of access to the system through the arm processor's ice interface. this feature is implemented via the register force ntrst (dbgu_fnr), that allows assertion of the ntrst signal of the ice interface. writing the bit fntrst (force ntrst) to 1 in this register prevents any activity on the tap controller. on standard devices, the bit fntrst resets to 0 and thus does not prevent ice access. this feature is especially useful on custom rom devices for customers who do not want their on-chip code to be visible.
188 at91sam7s64 preliminary 6070a?atarm?28-oct-04 debug unit user interface table 50. debug unit memory map offset register name access reset value 0x0000 control register dbgu_cr write-only ? 0x0004 mode register dbgu_mr read/write 0x0 0x0008 interrupt enable register dbgu_ier write-only ? 0x000c interrupt disable register dbgu_idr write-only ? 0x0010 interrupt mask register dbgu_imr read-only 0x0 0x0014 status register dbgu_sr read-only ? 0x0018 receive holding register dbgu_rhr read-only 0x0 0x001c transmit holding register dbgu_thr write-only ? 0x0020 baud rate generator register dbgu_brgr read/write 0x0 0x0024 - 0x003c reserved ? ? ? 0x0040 chip id register dbgu_cidr read-only ? 0x0044 chip id extension register dbgu_exid read-only ? 0x0048 force ntrst register dbgu_fnr read/write 0x0 0x004c - 0x00fc reserved ? ? ? 0x0100 - 0x0124 pdc area ? ? ?
189 at91sam7s64 preliminary 6070a?atarm?28-oct-04 debug unit control register name: dbgu_cr access type: write-only rstrx: reset receiver 0 = no effect. 1 = the receiver logic is reset and disabled. if a character is being received, the reception is aborted. rsttx: reset transmitter 0 = no effect. 1 = the transmitter logic is reset and disabled. if a character is being transmitted, the transmission is aborted. rxen: receiver enable 0 = no effect. 1 = the receiver is enabled if rxdis is 0. rxdis: receiver disable 0 = no effect. 1 = the receiver is disabled. if a character is being processed and rstrx is not set, the character is completed before the receiver is stopped. txen: transmitter enable 0 = no effect. 1 = the transmitter is enabled if txdis is 0. txdis: transmitter disable 0 = no effect. 1 = the transmitter is disabled. if a character is being processed and a character has been written the dbgu_thr and rsttx is not set, both characters are completed before the transmitter is stopped. rststa: reset status bits 0 = no effect. 1 = resets the status bits pare, frame and ovre in the dbgu_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????? rststa 76543210 txdis txen rxdis rxen rsttx rstrx ??
190 at91sam7s64 preliminary 6070a?atarm?28-oct-04 debug unit mode register name: dbgu_mr access type: read/write par: parity type chmode: channel mode 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 chmode ?? pa r ? 76543210 ???????? par parity type 000even parity 0 0 1 odd parity 0 1 0 space: parity forced to 0 0 1 1 mark: parity forced to 1 1xxno parity chmode mode description 0 0 normal mode 0 1 automatic echo 1 0 local loopback 1 1 remote loopback
191 at91sam7s64 preliminary 6070a?atarm?28-oct-04 debug unit interrupt enable register name: dbgu_ier access type: write-only rxrdy: enable rxrdy interrupt txrdy: enable txrdy interrupt endrx: enable end of receive transfer interrupt endtx: enable end of transmit interrupt ovre: enable overrun error interrupt frame: enable framing error interrupt pare: enable parity error interrupt txempty: enable txempty interrupt txbufe: enable buffer empty interrupt rxbuff: enable buffer full interrupt commtx: enable commtx (from arm) interrupt commrx: enable commrx (from arm) interrupt 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
192 at91sam7s64 preliminary 6070a?atarm?28-oct-04 debug unit interrupt disable register name: dbgu_idr access type: write-only rxrdy: disable rxrdy interrupt txrdy: disable txrdy interrupt endrx: disable end of receive transfer interrupt endtx: disable end of transmit interrupt ovre: disable overrun error interrupt frame: disable framing error interrupt pare: disable parity error interrupt txempty: disable txempty interrupt txbufe: disable buffer empty interrupt rxbuff: disable buffer full interrupt commtx: disable commtx (from arm) interrupt commrx: disable commrx (from arm) interrupt 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
193 at91sam7s64 preliminary 6070a?atarm?28-oct-04 debug unit interrupt mask register name: dbgu_imr access type: read-only rxrdy: mask rxrdy interrupt txrdy: disable txrdy interrupt endrx: mask end of receive transfer interrupt endtx: mask end of transmit interrupt ovre: mask overrun error interrupt frame: mask framing error interrupt pare: mask parity error interrupt txempty: mask txempty interrupt txbufe: mask txbufe interrupt rxbuff: mask rxbuff interrupt commtx: mask commtx interrupt commrx: mask commrx interrupt 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
194 at91sam7s64 preliminary 6070a?atarm?28-oct-04 debug unit status register name: dbgu_sr access type: read-only rxrdy: receiver ready 0 = no character has been received since the last read of the dbgu_rhr or the receiver is disabled. 1 = at least one complete character has been re ceived, transferred to dbgu_rhr and not yet read. txrdy: transmitter ready 0 = a character has been written to dbgu_thr and not yet transferred to the shift register, or the transmitter is disabled. 1 = there is no character written to dbgu_thr not yet transferred to the shift register. endrx: end of receiver transfer 0 = the end of transfer signal from the receiver peripheral data controller channel is inactive. 1 = the end of transfer signal from the receiver peripheral data controller channel is active. endtx: end of transmitter transfer 0 = the end of transfer signal from the transmitter peripheral data controller channel is inactive. 1 = the end of transfer signal from the transmitter peripheral data controller channel is active. ovre: overrun error 0 = no overrun error has occurred since the last rststa. 1 = at least one overrun error has occurred since the last rststa. frame: framing error 0 = no framing error has occurred since the last rststa. 1 = at least one framing error has occurred since the last rststa. pare: parity error 0 = no parity error has occurred since the last rststa. 1 = at least one parity error has occurred since the last rststa. txempty: transmitter empty 0 = there are characters in dbgu_thr, or characters being processed by the transmitter, or the transmitter is disabled. 1 = there are no characters in dbgu_thr and there are no characters being processed by the transmitter. txbufe: transmission buffer empty 0 = the buffer empty signal from the transmitter pdc channel is inactive. 1 = the buffer empty signal from the transmitter pdc channel is active. rxbuff: receive buffer full 0 = the buffer full signal from the receiver pdc channel is inactive. 1 = the buffer full signal from the receiver pdc channel is active. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy
195 at91sam7s64 preliminary 6070a?atarm?28-oct-04 commtx: debug communication channel write status 0 = commtx from the arm processor is inactive. 1 = commtx from the arm processor is active. commrx: debug communication channel read status 0 = commrx from the arm processor is inactive. 1 = commrx from the arm processor is active.
196 at91sam7s64 preliminary 6070a?atarm?28-oct-04 debug unit receiver holding register name: dbgu_rhr access type: read-only rxchr: received character last received character if rxrdy is set. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rxchr
197 at91sam7s64 preliminary 6070a?atarm?28-oct-04 debug unit transmit holding register name: dbgu_thr access type: write-only txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. debug unit baud rate generator register name: dbgu_brgr access type: read/write cd: clock divisor 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 txchr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cd 76543210 cd cd baud rate clock 0 disabled 1mck 2 to 65535 mck / (cd x 16)
198 at91sam7s64 preliminary 6070a?atarm?28-oct-04 debug unit chip id register name: dbgu_cidr access type: read-only version: version of the device eproc: embedded processor nvpsiz: nonvolatile program memory size 31 30 29 28 27 26 25 24 ext nvptyp arch 23 22 21 20 19 18 17 16 arch sramsiz 15 14 13 12 11 10 9 8 nvpsiz2 nvpsiz 76543210 eproc version eproc processor 0 0 1 arm946es 0 1 0 arm7tdmi 1 0 0 arm920t 1 0 1 arm926ejs nvpsiz size 0000none 00018k bytes 001016k bytes 001132k bytes 0100reserved 010164k bytes 0110reserved 0111128k bytes 1000reserved 1001256k bytes 1010512k bytes 1011reserved 1 1 0 0 1024k bytes 1101reserved 1 1 1 0 2048k bytes 1111reserved
199 at91sam7s64 preliminary 6070a?atarm?28-oct-04 nvpsiz2: second nonvolatile program memory size sramsiz: internal sram size nvpsiz2 size 0000none 00018k bytes 001016k bytes 001132k bytes 0100reserved 010164k bytes 0110reserved 0111128k bytes 1000reserved 1001256k bytes 1010512k bytes 1011reserved 1 1 0 0 1024k bytes 1101reserved 1 1 1 0 2048k bytes 1111reserved sramsiz size 0000reserved 00011k bytes 00102k bytes 0011reserved 0100reserved 01014k bytes 0110reserved 0111160k bytes 10008k bytes 100116k bytes 101032k bytes 101164k bytes 1100128k bytes 1101256k bytes 111096k bytes 1111512k bytes
200 at91sam7s64 preliminary 6070a?atarm?28-oct-04 arch: architecture identifier nvptyp: nonvolatile program memory type ext: extension flag 0 = chip id has a single register definition without extension 1 = an extended chip id exists. arch architecture hex bin 0x40 0100 0000 at91x40 series 0x63 0110 0011 at91x63 series 0x55 0101 0101 at91x55 series 0x42 0100 0010 at91x42 series 0x92 1001 0010 at91x92 series 0x34 0011 0100 at91x34 series 0x70 0111 0000 at91sam7sxx and at91sam7axx series 0x71 0111 0001 at91sam7xxx series 0x72 0111 0010 at91sam7exx series 0x73 0111 0011 at91sam7lxx series 0x19 0001 1001 at91sam9xx series nvptyp memory 000rom 0 0 1 romless or on-chip flash 1 0 0 sram emulating rom 0 1 0 embedded flash memory 0 1 1 rom and embedded flash memory nvpsiz is rom size nvpsiz2 is flash size
201 at91sam7s64 preliminary 6070a?atarm?28-oct-04 debug unit chip id extension register name: dbgu_exid access type: read-only exid: chip id extension reads 0 if the bit ext in dbgu_cidr is 0. debug unit force ntrst register name: dbgu_fnr access type: read/write fntrst: force ntrst 0 = ntrst of the arm processor?s tap controller is driven by the ice_nreset signal. 1 = ntrst of the arm processor?s tap controller is held low. 31 30 29 28 27 26 25 24 exid 23 22 21 20 19 18 17 16 exid 15 14 13 12 11 10 9 8 exid 76543210 exid 31 30 29 28 27 26 25 24 ??????? ? 23 22 21 20 19 18 17 16 ??????? ? 15 14 13 12 11 10 9 8 ??????? ? 7654321 0 ??????? fntrst
202 at91sam7s64 preliminary 6070a?atarm?28-oct-04
203 at91sam7s64 preliminary 6070a?atarm?28-oct-04 parallel input/output controller (pio) overview the parallel input/output controller (pio) manages up to 32 fully programmable input/output lines. each i/o line may be dedicated as a general-purpose i/o or be assigned to a function of an embedded peripheral. this assures effective optimization of the pins of a product. each i/o line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user interface. each i/o line of the pio controller features: an input change interrupt enabling level change detection on any i/o line. a glitch filter providing rejection of pulses lower than one-half of clock cycle. multi-drive capability similar to an open drain i/o line. control of the the pull-up of the i/o line. input visibility and output control. the pio controller also features a synchronous output providing up to 32 bits of data output in a single write operation.
204 at91sam7s64 preliminary 6070a?atarm?28-oct-04 block diagram figure 75. block diagram application block diagram figure 76. application block diagram embedded peripheral embedded peripheral pio interrupt pio controller up to 32 pins pmc up to 32 peripheral ios up to 32 peripheral ios pio clock apb aic data, enable pin 31 pin 1 pin 0 data, enable on-chip peripherals pio controller on-chip peripheral drivers control & command driver keyboard driver keyboard driver general purpose i/os external devices
205 at91sam7s64 preliminary 6070a?atarm?28-oct-04 product dependencies pin multiplexing each pin is configurable, according to product definition as either a general-purpose i/o line only, or as an i/o line multiplexed with one or two peripheral i/os. as the multiplexing is hard- ware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the pio controllers required by their application. when an i/o line is general-purpose only, i.e. not multiplexed with any peripheral i/o, programming of the pio controller regarding the assignment to a peripheral has no effect and only the pio controller can control how the pin is driven by the product. external interrupt lines the interrupt signals fiq and irq0 to irqn are most generally multiplexed through the pio controllers. however, it is not necessary to assign the i/o line to the interrupt function as the pio controller has no effect on inputs and the interrupt lines (fiq or irqs) are used only as inputs. power management the power management controller controls the pio controller clock in order to save power. writing any of the registers of the user interface does not require the pio controller clock to be enabled. this means that the configuration of the i/o lines does not require the pio controller clock to be enabled. however, when the clock is disabled, not all of the features of the pio controller are available. note that the input change interrupt and the read of the pin level require the clock to be validated. after a hardware reset, the pio clock is disabled by default. the user must configure the power management controller before any access to the input line information. interrupt generation for interrupt handling, the pio controllers are considered as user peripherals. this means that the pio controller interrupt lines are connected among the interrupt sources 2 to 31. refer to the pio controller peripheral identifier in the product description to identify the inter- rupt sources dedicated to the pio controllers. the pio controller interrupt can be generated only if the pio controller clock is enabled.
206 at91sam7s64 preliminary 6070a?atarm?28-oct-04 functional description the pio controller features up to 32 fully-programmable i/o lines. most of the control logic associated to each i/o is represented in figure 77. in this description each signal shown rep- resents but one of up to 32 possible indexes. figure 77. i/o line control logic pull-up resistor control each i/o line is designed with an embedded pull-up resistor. the value of this resistor is about 100 k ? (see the product electrical characteristics for more details about this value). the pull- 1 0 1 0 1 0 glitch filter peripheral b input peripheral a input 1 0 pio_ifdr[0] pio_ifsr[0] pio_ifer[0] edge detector pio_pdsr[0] pio_isr[0] pio_idr[0] pio_imr[0] pio_ier[0] pio interrupt (up to 32 possible inputs) pio_isr[31] pio_idr[31] pio_imr[31] pio_ier[31] pad 1 0 pio_pudr[0] pio_pusr[0] pio_puer[0] pio_mddr[0] pio_mdsr[0] pio_mder[0] pio_codr[0] pio_odsr[0] pio_sodr[0] pio_pdr[0] pio_psr[0] pio_per[0] 1 0 1 0 pio_bsr[0] pio_absr[0] pio_asr[0] peripheral b output enable peripheral a output enable peripheral b output peripheral a output pio_odr[0] pio_osr[0] pio_oer[0]
207 at91sam7s64 preliminary 6070a?atarm?28-oct-04 up resistor can be enabled or disabled by writing respectively pio_puer (pull-up enable register) and pio_pudr (pull-up disable resisto r). writing in these registers results in set- ting or clearing the corresponding bit in pio_pusr (pull-up status register). reading a 1 in pio_pusr means the pull-up is disabled and reading a 0 means the pull-up is enabled. control of the pull-up resistor is possible regardless of the configuration of the i/o line. after reset, all of the pull-ups are enabled, i.e. pio_pusr resets at the value 0x0. i/o line or peripheral function selection when a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers pio_per (pio enable register) and pio_pdr (pio disable register). the reg- ister pio_psr (pio status register) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the pio controller. a value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the pio_absr (ab select status register). a value of 1 indicates the pin is controlled by the pio controller. if a pin is used as a general purpose i/o line (not multiplexed with an on-chip peripheral), pio_per and pio_pdr have no effect and pio_psr returns 1 for the corresponding bit. after reset, most generally, the i/o lines are controlled by the pio controller, i.e. pio_psr resets at 1. however, in some events, it is important that pio lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). thus, the reset value of pio_psr is defined at the product level, depending on the multiplexing of the device. peripheral a or b selection the pio controller provides multiplexing of up to two peripheral functions on a single pin. the selection is performed by writing pio_asr (a select register) and pio_bsr (select b regis- ter). pio_absr (ab select status register) indicates which peripheral line is currently selected. for each pin, the corresponding bit at level 0 means peripheral a is selected whereas the corresponding bit at level 1 indicates that peripheral b is selected. note that multiplexing of peripheral lines a and b only affects the output line. the peripheral input lines are always connected to the pin input. after reset, pio_absr is 0, thus indicating that all the pio lines are configured on peripheral a. however, peripheral a generally does not drive the pin as the pio controller resets in i/o line mode. writing in pio_asr and pio_bsr manages pio_absr regardless of the configuration of the pin. however, assignment of a pin to a peripheral function requires a write in the correspond- ing peripheral selection register (pio_asr or pio_bsr) in addition to a write in pio_pdr. output control when the i/0 line is assigned to a peripheral function, i.e. the corresponding bit in pio_psr is at 0, the drive of the i/o line is controlled by the peripheral. peripheral a or b, depending on the value in pio_absr, determines whether the pin is driven or not. when the i/o line is controlled by the pio controller, the pin can be configured to be driven. this is done by writing pio_oer (output enable register) and pio_pdr (output disable register). the results of these write operations are detected in pio_osr (output status reg- ister). when a bit in this register is at 0, the corresponding i/o line is used as an input only. when the bit is at 1, the corresponding i/o line is driven by the pio controller. the level driven on an i/o line can be determined by writing in pio_sodr (set output data register) and pio_codr (clear output data register). these write operations respectively set and clear pio_odsr (output data status register), which represents the data driven on
208 at91sam7s64 preliminary 6070a?atarm?28-oct-04 the i/o lines. writing in pio_oer and pio_odr manages pio_osr whether the pin is con- figured to be controlled by the pio controller or assigned to a peripheral function. this enables configuration of the i/o line prior to setting it to be managed by the pio controller. similarly, writing in pio_sodr and pio_codr effects pio_odsr. this is important as it defines the first level driven on the i/o line. synchronous data output controlling all parallel busses using several pios requires two successive write operations in the pio_sodr and pio_codr registers. this may lead to unexpected transient values. the pio controller offers a direct control of pio outputs by single write access to pio_odsr (out- put data status register). only bits unmasked by pio_oswsr (output write status register) are written. the mask bits in the pio_owsr are set by writing to pio_ower (out- put write enable register) and cleared by writing to pio_owdr (output write disable register). after reset, the synchronous data output is disabled on all the i/o lines as pio_owsr resets at 0x0. multi drive control (open drain) each i/o can be independently programmed in open drain by using the multi drive feature. this feature permits several drivers to be connected on the i/o line which is driven low only by each device. an external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line. the multi drive feature is controlled by pio_mder (multi-driver enable register) and pio_mddr (multi-driver disable register). the multi drive can be selected whether the i/o line is controlled by the pio controller or assigned to a peripheral function. pio_mdsr (multi- driver status register) indicates the pins that are configured to support external drivers. after reset, the multi drive feature is disabled on all pins, i.e. pio_mdsr resets at value 0x0. output line timings figure 78 shows how the outputs are driven either by writing pio_sodr or pio_codr, or by directly writing pio_odsr. this last case is valid only if the corresponding bit in pio_owsr is set. figure 78 also shows when the feedback in pio_pdsr is available. figure 78. output line timings inputs the level on each i/o line can be read through pio_pdsr (peripheral data status register). this register indicates the level of the i/o lines regardless of their configuration, whether uniquely as an input or driven by the pio controller or driven by a peripheral. 2 cycles apb access 2 cycles apb access mck write pio_sodr write pio_odsr at 1 pio_odsr pio_pdsr write pio_codr write pio_odsr at 0
209 at91sam7s64 preliminary 6070a?atarm?28-oct-04 reading the i/o line levels requires the clock of the pio controller to be enabled, otherwise pio_pdsr reads the levels present on the i/o line at the time the clock was disabled. input glitch filtering optional input glitch filters are independently programmable on each i/o line. when the glitch filter is enabled, a glitch with a duration of less than 1/2 master clock (mck) cycle is automat- ically rejected, while a pulse with a duration of 1 master clock cycle or more is accepted. for pulse durations between 1/2 master clock cycle and 1 master clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. thus for a pulse to be visible it must exceed 1 master clock cycle, whereas for a glitch to be reliably fil- tered out, its duration must not exceed 1/2 master clock cycle. the filter introduces one master clock cycle latency if the pin level change occurs before a rising edge. however, this latency does not appear if the pin level change o ccurs before a falling edge. this is illustrated in figure 79. the glitch filters are controlled by the register set; pio_ifer (input filter enable register), pio_ifdr (input filter disable register) and pio_ifsr (input filter status register). writing pio_ifer and pio_ifdr respectively sets and clears bits in pio_ifsr. this last register enables the glitch filter on the i/o lines. when the glitch filter is enabled, it does not modify the behavior of the inputs on the peripher- als. it acts only on the value read in pio_pdsr and on the input change interrupt detection. the glitch filters require that the pio controller clock is enabled. figure 79. input glitch filter timing input change interrupt the pio controller can be programmed to generate an interrupt when it detects an input change on an i/o line. the input change interrupt is controlled by writing pio_ier (interrupt enable register) and pio_idr (interrupt disable register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in pio_imr (interrupt mask register). as input change detection is possible only by comparing two suc- cessive samplings of the input of the i/o line, the pio controller clock must be enabled. the input change interrupt is available, regardless of the configuration of the i/o line, i.e. config- ured as an input only, controlled by the pio controller or assigned to a peripheral function. when an input change is detected on an i/o line, the corresponding bit in pio_isr (interrupt status register) is set. if the corresponding bit in pio_imr is set, the pio controller interrupt line is asserted. the interrupt signals of the thirty-two channels are ored-wired together to generate a single interrupt signal to the advanced interrupt controller. when the software reads pio_isr, all the interrupts are automatically cleared. this signifies that all the interrupts that are pending when pio_isr is read must be handled. mck pin level pio_pdsr if pio_ifsr = 0 pio_pdsr if pio_ifsr = 1 1 cycle 1 cycle 1 cycle up to 1.5 cycles 2 cycles up to 2.5 cycles up to 2 cycles 1 cycle 1 cycle
210 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 80. input change interrupt timings mck pin level read pio_isr apb access pio_isr apb access
211 at91sam7s64 preliminary 6070a?atarm?28-oct-04 i/o lines programming example the programing example as shown in table 51 below is used to define the following configuration. 4-bit output port on i/o lines 0 to 3, (should be written in a single write operation), open- drain, with pull-up resistor four output signals on i/o lines 4 to 7 (to drive leds for example), driven high and low, no pull-up resistor four input signals on i/o lines 8 to 11 (to read push-button states for example), with pull- up resistors, glitch filters and input change interrupts four input signals on i/o line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter i/o lines 16 to 19 assigned to peripheral a functions with pull-up resistor i/o lines 20 to 23 assigned to peripheral b functions, no pull-up resistor i/o line 24 to 27 assigned to peripheral a with input change interrupt and pull-up resistor table 51. programming example register value to be written pio_per 0x0000 ffff pio_pdr 0x0fff 0000 pio_oer 0x0000 00ff pio_odr 0x0fff ff00 pio_ifer 0x0000 0f00 pio_ifdr 0x0fff f0ff pio_sodr 0x0000 0000 pio_codr 0x0fff ffff pio_ier 0x0f00 0f00 pio_idr 0x00ff f0ff pio_mder 0x0000 000f pio_mddr 0x0fff fff0 pio_pudr 0x00f0 00f0 pio_puer 0x0f0f ff0f pio_asr 0x0f0f 0000 pio_bsr 0x00f0 0000 pio_ower 0x0000 000f pio_owdr 0x0fff fff0
212 at91sam7s64 preliminary 6070a?atarm?28-oct-04 parallel input/output controller (pio) user interface each i/o line controlled by the pio controller is associated with a bit in each of the pio con- troller user interface registers. each register is 32 bits wide. if a parallel i/o line is not defined, writing to the corresponding bits has no effect. undefined bits read zero. if the i/o line is not multiplexed with any peripheral, the i/o line is controlled by the pio controller and pio_psr returns 1 systematically. table 52. parallel input/output controller (pio) register mapping offset register name access reset value 0x0000 pio enable register pio_per write-only ? 0x0004 pio disable register pio_pdr write-only ? 0x0008 pio status register (1) pio_psr read-only 0x0000 0000 0x000c reserved 0x0010 output enable register pio_oer write-only ? 0x0014 output disable register pio_odr write-only ? 0x0018 output status register pio_osr read-only 0x0000 0000 0x001c reserved 0x0020 glitch input filter enable register pio_ifer write-only ? 0x0024 glitch input filter disable register pio_ifdr write-only ? 0x0028 glitch input filter status register pio_ifsr read-only 0x0000 0000 0x002c reserved 0x0030 set output data register pio_sodr write-only ? 0x0034 clear output data register pio_codr write-only ? 0x0038 output data status register (2) pio_odsr read-only 0x0000 0000 0x003c pin data status register (3) pio_pdsr read-only 0x0040 interrupt enable register pio_ier write-only ? 0x0044 interrupt disable register pio_idr write-only ? 0x0048 interrupt mask register pio_imr read-only 0x00000000 0x004c interrupt status register (4) pio_isr read-only 0x00000000 0x0050 multi-driver enable register pio_mder write-only ? 0x0054 multi-driver disable register pio_mddr write-only ? 0x0058 multi-driver status register pio_mdsr read-only 0x00000000 0x005c reserved 0x0060 pull-up disable register pio_pudr write-only ? 0x0064 pull-up enable register pio_puer write-only ? 0x0068 pad pull-up status register pio_pusr read-only 0x00000000 0x006c reserved
213 at91sam7s64 preliminary 6070a?atarm?28-oct-04 notes: 1. reset value of pio_psr depends on the product implementation. 2. pio_odsr is read-only or read/write depending on pio_owsr i/o lines. 3. reset value of pio_pdsr depends on the level of the i/o lines. 4. pio_isr is reset at 0x0. however, the first read of the register may read a different value as input changes may have occurred. 5. only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the secon d register. 0x0070 peripheral a select register (5) pio_asr write-only ? 0x0074 peripheral b select register (5) pio_bsr write-only ? 0x0078 ab status register (5) pio_absr read-only 0x00000000 0x007c - 0x009c reserved 0x00a0 output write enable pio_ower write-only ? 0x00a4 output write disable pio_owdr write-only ? 0x00a8 output write status register pio_owsr read-only 0x00000000 0x00ac - 0x00fc reserved table 52. parallel input/output controller (pio) register mapping (continued) offset register name access reset value
214 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pio controller pio enable register name: pio_per access type: write-only p0-p31: pio enable 0 = no effect. 1 = enables the pio to control the corresponding pin (disables peripheral control of the pin). pio controller pio disable register name: pio_pdr access type: write-only p0-p31: pio disable 0 = no effect. 1 = disables the pio from controlling the corresponding pin (enables peripheral control of the pin). 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
215 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pio controller pio status register name: pio_psr access type: read-only p0-p31: pio status 0 = pio is inactive on the corresponding i/o line (peripheral is active). 1 = pio is active on the corresponding i/o line (peripheral is inactive). pio controller output enable register name: pio_oer access type: write-only p0-p31: output enable 0 = no effect. 1 = enables the output on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
216 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pio controller output disable register name: pio_odr access type: write-only p0-p31: output disable 0 = no effect. 1 = disables the output on the i/o line. pio controller output status register name: pio_osr access type: read-only p0-p31: output status 0 = the i/o line is a pure input. 1 = the i/o line is enabled in output. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
217 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pio controller input filter enable register name: pio_ifer access type: write-only p0-p31: input filter enable 0 = no effect. 1 = enables the input glitch filter on the i/o line. pio controller input filter disable register name: pio_ifdr access type: write-only p0-p31: input filter disable 0 = no effect. 1 = disables the input glitch filter on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
218 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pio controller input filter status register name: pio_ifsr access type: read-only p0-p31: input filer status 0 = the input glitch filter is disabled on the i/o line. 1 = the input glitch filter is enabled on the i/o line. pio controller set output data register name: pio_sodr access type: write-only p0-p31: set output data 0 = no effect. 1 = sets the data to be driven on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
219 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pio controller clear output data register name: pio_codr access type: write-only p0-p31: set output data 0 = no effect. 1 = clears the data to be driven on the i/o line. pio controller output data status register name: pio_odsr access type: read-only or read/write p0-p31: output data status 0 = the data to be driven on the i/o line is 0. 1 = the data to be driven on the i/o line is 1. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
220 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pio controller pin data status register name: pio_pdsr access type: read-only p0-p31: output data status 0 = the i/o line is at level 0. 1 = the i/o line is at level 1. pio controller interrupt enable register name: pio_ier access type: write-only p0-p31: input change interrupt enable 0 = no effect. 1 = enables the input change interrupt on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
221 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pio controller interrupt disable register name: pio_idr access type: write-only p0-p31: input change interrupt disable 0 = no effect. 1 = disables the input change interrupt on the i/o line. pio controller interrupt mask register name: pio_imr access type: read-only p0-p31: input change interrupt mask 0 = input change interrupt is disabled on the i/o line. 1 = input change interrupt is enabled on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
222 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pio controller interrupt status register name: pio_isr access type: read-only p0-p31: input change interrupt status 0 = no input change has been detected on the i/o line since pio_isr was last read or since reset. 1 = at least one input change has been detected on the i/o line since pio_isr was last read or since reset. pio multi-driver enable register name: pio_mder access type: write-only p0-p31: multi drive enable. 0 = no effect. 1 = enables multi drive on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
223 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pio multi-driver disable register name: pio_mddr access type: write-only p0-p31: multi drive disable. 0 = no effect. 1 = disables multi drive on the i/o line. pio multi-driver status register name: pio_mdsr access type: read-only p0-p31: multi drive status. 0 = the multi drive is disabled on the i/o line. the pin is driven at high and low level. 1 = the multi drive is enabled on the i/o line. the pin is driven at low level only. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
224 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pio pull up disable register name: pio_pudr access type: write-only p0-p31: pull up disable. 0 = no effect. 1 = disables the pull up resistor on the i/o line. pio pull up enable register name: pio_puer access type: write-only p0-p31: pull up enable. 0 = no effect. 1 = enables the pull up resistor on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
225 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pio pull up status register name: pio_pusr access type: read-only p0-p31: pull up status. 0 = pull up resistor is enabled on the i/o line. 1 = pull up resistor is disabled on the i/o line. pio peripheral a select register name: pio_asr access type: write-only p0-p31: peripheral a select. 0 = no effect. 1 = assigns the i/o line to the peripheral a function. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
226 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pio peripheral b select register name: pio_bsr access type: write-only p0-p31: peripheral b select. 0 = no effect. 1 = assigns the i/o line to the peripheral b function. pio peripheral a b status register name: pio_absr access type: read-only p0-p31: peripheral a b status. 0 = the i/o line is assigned to the peripheral a. 1 = the i/o line is assigned to the peripheral b. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
227 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pio output write enable register name: pio_ower access type: write-only p0-p31: output write enable. 0 = no effect. 1 = enables writing pio_odsr for the i/o line. pio output write disable register name: pio_owdr access type: write-only p0-p31: output write disable. 0 = no effect. 1 = disables writing pio_odsr for the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
228 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pio output write status register name: pio_owsr access type: read-only p0-p31: output write status. 0 = writing pio_odsr does not affect the i/o line. 1 = writing pio_odsr affects the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
229 at91sam7s64 preliminary 6070a?atarm?28-oct-04 serial peripheral interface (spi) overview the serial peripheral interface (spi) circuit is a synchronous serial data link that provides communication with external devices in master or slave mode. it also enables communication between processors if an external processor is connected to the system. the serial peripheral interface is essentially a shift register that serially transmits data bits to other spis. during a data transfer, one spi system acts as the ?master?' which controls the data flow, while the other devices act as ?slaves'' which have data shifted into and out by the master. different cpus can take turn being masters (multiple master protocol opposite to sin- gle master protocol where one cpu is always the master while all of the others are always slaves) and one master may simultaneously shift data into multiple slaves. however, only one slave may drive its output to write data back to the master at any given time. a slave device is selected when the master asserts its nss signal. if multiple slave devices exist, the master generates a separate slave select signal for each slave (npcs). the spi system consists of two data lines and two control lines: master out slave in (mosi): this data line supplies the output data from the master shifted into the input(s) of the slave(s). master in slave out (miso): this data line supplies the output data from a slave to the input of the master. there may be no more than one slave transmitting data during any particular transfer. serial clock (spck): this control line is driven by the master and regulates the flow of the data bits. the master may transmit data at a variety of baud rates; the spck line cycles once for each bit that is transmitted. slave select (nss): this control line allows slaves to be turned on and off by hardware.
230 at91sam7s64 preliminary 6070a?atarm?28-oct-04 block diagram figure 81. block diagram note: 1. n = 32 application block diagram figure 82. application block diagram: single master/multiple slave implementation spi interface interrupt control pio pdc pmc mck spi interrupt spck miso mosi npcs0/nss npcs1 npcs2 div npcs3 apb mck n (1) spi master spck miso mosi npcs0 npcs1 npcs2 spck miso mosi nss slave 0 spck miso mosi nss slave 1 spck miso mosi nss slave 2 nc npcs3
231 at91sam7s64 preliminary 6070a?atarm?28-oct-04 signal description product dependencies i/o lines the pins used for interfacing the compliant external devices may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the spi pins to their peripheral functions. power management the spi may be clocked through the power management controller (pmc), thus the program- mer must first configure the pmc to enable the spi clock. interrupt the spi interface has an interrupt line connected to the advanced interrupt controller (aic). handling the spi interrupt requires programming the aic before configuring the spi. table 53. signal description pin name pin description type master slave miso master in slave out input output mosi master out slave in output input spck serial clock output input npcs1-npcs3 peripheral chip selects output unused npcs0/nss peripheral chip select/slave select output input
232 at91sam7s64 preliminary 6070a?atarm?28-oct-04 functional description modes of operation the spi operates in master mode or in slave mode. operation in master mode is programmed by writing at 1 the mstr bit in the mode register. the pins npcs0 to npcs3 are all configured as outputs, the spck pin is driven, the miso line is wired on the receiver input and the mosi line driven as an output by the transmitter. if the mstr bit is written at 0, the spi operates in slave mode. the miso line is driven by the transmitter output, the mosi line is wired on the receiver input, the spck pin is driven by the transmitter to synchronize the receiver. the npcs0 pin becomes an input, and is used as a slave select signal (nss). the pins npcs1 to npcs3 are not driven and can be used for other purposes. the data transfers are identically programmable for both modes of operations. the baud rate generator is activated only in master mode. data transfer four combinations of polarity and phase are available for data transfers. the clock polarity is programmed with the cpol bit in the chip select register. the clock phase is programmed with the ncpha bit. these two parameters determine the edges of the clock signal on which data is driven and sampled. each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. thus, a master/slave pair must use the same parameter pair values to communicate. if multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to com- municate with a different slave. table 54 shows the four modes and corresponding parameter settings. figure 83 and figure 84 show examples of data transfers. table 54. spi bus protocol mode spi mode cpol cpha 001 100 211 310
233 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 83. spi transfer format (ncpha = 1, 8 bits per transfer) figure 84. spi transfer format (ncpha = 0, 8 bits per transfer) 6 * spck (cpol = 0) spck (cpol = 1) mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) msb msb lsb lsb 6 6 5 5 4 4 3 3 2 2 1 1 * not defined, but normally msb of previous character received. 1 2345 78 6 * spck (cpol = 0) spck (cpol = 1) 1 2345 7 mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) 8 msb msb lsb lsb 6 6 5 5 4 4 3 3 1 1 * not defined but normally lsb of previous character transmitted. 2 2 6
234 at91sam7s64 preliminary 6070a?atarm?28-oct-04 master mode operations when configured in master mode, the spi operates on the clock generated by the internal pro- grammable baud rate generator. it fully controls the data transfers to and from the slave(s) connected to the spi bus. the spi drives the chip select line to the slave and the serial clock signal (spck). the spi features two holding registers, the transmit data register and the receive data reg- ister, and a single shift register. the holding registers maintain the data flow at a constant rate. after enabling the spi, a data transfer begins when the processor writes to the spi_tdr (transmit data register). the written data is immediately transferred in the shift register and transfer on the spi bus starts. while the data in the shift register is shifted on the mosi line, the miso line is sampled and shifted in the shift register. transmission cannot occur without reception. no transfer is started when writing into the spi_tdr if the pcs field does not select a slave. the pcs field is set by writing the spi_tdr in variable mode, or the spi_mr in fixed mode, depending on the value of pcs field. if new data is written in spi_tdr during the transfer, it stays in it until the current transfer is completed. then, the received data is transferred from the shift register to spi_rdr, the data in spi_tdr is loaded in the shift register and a new transfer starts. the transfer of a data written in spi_tdr in the shift register is indicated by the tdre bit (transmit data register empty) in the status register (spi_sr). when new data is written in spi_tdr, this bit is cleared. the tdre bit is used to trigger the transmit pdc channel. the end of transfer is indicated by the txempty flag in the spi_sr register. if a transfer delay (dlybct) is greater than 0 for the last transfer, txempty is set after the completion of said delay. the master clock (mck) can be switched off at this time. the transfer of received data from the shift regi ster in spi_rdr is indicated by the rdrf bit (receive data register full) in the status register (spi_sr). when the received data is read, the rdrf bit is cleared. if the spi_rdr (receive data register) has not been read before new data is received, the overrun error bit (ovres) in spi_sr is set. as long as this flag is set, no data is loaded in spi_rdr. the user has to read the stat us register to clear the ovres bit. figure 85 on page 235 shows a block diagram of the spi when operating in master mode. fig- ure 86 on page 236 shows a flow chart describing how transfers are handled.
235 at91sam7s64 preliminary 6070a?atarm?28-oct-04 master mode block diagram figure 85. master mode block diagram shift register spck mosi lsb msb miso spi_rdr rd spi clock tdre spi_tdr td rdrf ovres spi_csr0..3 cpol ncpha bits 0 1 fdiv mck mck/n baud rate generator spi_csr0..3 scbr npcs3 npcs0 npcs2 npcs1 npcs0 0 1 ps spi_mr pcs spi_tdr pcs modf current peripheral spi_rdr pcs spi_csr0..3 csaat pcsdec modfdis mstr
236 at91sam7s64 preliminary 6070a?atarm?28-oct-04 master mode flow diagram figure 86. master mode flow diagram s spi enable csaat ? ps ? 1 0 0 1 1 npcs = spi_tdr(pcs) npcs = spi_mr(pcs) delay dlybs serializer = spi_tdr(td) tdre = 1 data transfer spi_rdr(rd) = serializer rdrf = 1 tdre ? npcs = 0xf delay dlybcs fixed peripheral variable peripheral delay dlybct 0 1 csaat ? 0 tdre ? 1 0 ps ? 0 1 spi_tdr(pcs) = npcs ? no yes spi_mr(pcs) = npcs ? no npcs = 0xf delay dlybcs npcs = spi_tdr(pcs) npcs = 0xf delay dlybcs npcs = spi_mr(pcs), spi_tdr(pcs) fixed peripheral variable peripheral - npcs defines the current chip select - csaat, dlybs, dlybct refer to the fields of the chip select register corresponding to the current chip select - when npcs is 0xf, csaat is 0.
237 at91sam7s64 preliminary 6070a?atarm?28-oct-04 clock generation the spi baud rate clock is generated by dividing the master clock (mck) or the master clock divided by 32, by a value between 2 and 255. the selection between master clock or master clock divided by n is done by the fdiv value set in the mode register this allows a maximum operating baud rate at up to master clock/2 and a minimum operating baud rate of mck divided by 255*32. programming the scbr field at 0 is forbidden. triggering a transfer while scbr is at 0 can lead to unpredictable results. at reset, scbr is 0 and the user has to program it at a valid value before performing the first transfer. the divisor can be defined independently for each chip select, as it has to be programmed in the scbr field of the chip select registers. this allows the spi to automatically adapt the baud rate for each interfaced peripheral without reprogramming. transfer delays figure 87 shows a chip select transfer change and consecutive transfers on the same chip select. three delays can be programmed to modify the transfer waveforms: the delay between chip selects, programmable only once for all the chip selects by writing the dlybcs field in the mode register. allows insertion of a delay between release of one chip select and before assertion of a new one. the delay before spck, independently programmable for each chip select by writing the field dlybs. allows the start of spck to be delayed after the chip select has been asserted. the delay between consecutive transfers, independently programmable for each chip select by writing the dlybct field. allows insertion of a delay between two transfers occurring on the same chip select these delays allow the spi to be adapted to the interfaced peripherals and their speed and bus release time. figure 87. programmable delays peripheral selection the serial peripherals are selected through the assertion of the npcs0 to npcs3 signals. by default, all the npcs signals are high before and after each transfer. the peripheral selection can be performed in two different ways: fixed peripheral select: spi exchanges data with only one peripheral variable peripheral select: data can be exchanged with more than one peripheral dlybcs dlybs dlybct dlybct chip select 1 chip select 2 spck
238 at91sam7s64 preliminary 6070a?atarm?28-oct-04 fixed peripheral select is activated by writing the ps bit to zero in spi_mr (mode register). in this case, the current peripheral is defined by the pcs field in spi_mr and the pcs fields of the chip select registers have no effect. variable peripheral select is activated by setting ps bit to one. the pcs field in spi_tdr is used to select the current peripheral. this means that the peripheral selection can be defined for each new data. the fixed peripheral selection allows buffer transfers with a single peripheral. using the pdc is an optimal means, as the size of the data transfer between the memory and the spi is either 8 bits or 16 bits. however, changing the peripheral selection requires the mode register to be reprogrammed. the variable peripheral selection allows buffer transfers with multiple peripherals without reprogramming the mode register. data written in spi_tdr is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. using the pdc in this mode requires 32-bit wide buffers, with the data in the lsbs and the pcs and lastxfer fields in the msbs, however the spi still controls the number of bits (8 to16) to be transferred through miso and mosi lines with the chip select configuration registers. this is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. peripheral chip select decoding the user can program the spi to operate with up to 15 peripherals by decoding the four chip select lines, npcs0 to npcs3 with an external logic. this can be enabled by writing the pcs- dec bit at 1 in the mode register (spi_mr). when operating without decoding, the spi makes sure that in any case only one chip select line is activated, i.e. driven low at a time. if two bits are defined low in a pcs field, only the low- est numbered chip select is driven low. when operating with decoding, the spi directly outputs the value defined by the pcs field of either the mode register or the transmit data register (depending on ps). as the spi sets a default value of 0xf on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. the spi has only four chip select registers, not 15. as a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. as an example, spi_crs0 defines the characteristics of the externally decoded peripherals 0 to 3, corre- sponding to the pcs values 0x0 to 0x3. thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. peripheral deselection when operating normally, as soon as the transfer of the last data written in spi_tdr is com- pleted, the npcs lines all rise. this might lead to runtime error if the processor is too long in responding to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers. to facilitate interfacing with such devices, the chip select register can be programmed with the csaat bit (chip select active after transfer) at 1. this allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. figure 88 shows different peripheral deselection cases and the effect of the csaat bit.
239 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 88. peripheral deselection mode fault detection a mode fault is detected when the spi is programmed in master mode and a low level is driven by an external master on the npcs0/nss signal. as this pin is generally configured in open-drain, it is important that a pull up resistor is connected on the npcs0 line, so that a high level is guaranteed and no spurious mode fault is detected. when a mode fault is detected, the modf bit in the spi_sr is set until the spi_sr is read and the spi is automatically disabled until re-enabled by writing the spien bit in the spi_cr (control register) at 1. by default, the mode fault detection circuitry is enabled. the user can disable mode fault detection by setting the modfdis bit in the spi mode register (spi_mr). spi slave mode when operating in slave mode, the spi processes data bits on the clock provided on the spi clock pin (spck). the spi waits for nss to go active before receiving the serial clock from an external master. when nss falls, the clock is validated on the serializer, which processes the number of bits defined by the bits field of the chip select register 0 (spi_csr0). these bits are processed following a phase and a polarity defined respectively by the ncpha and cpol bits of the spi_csr0. note that bits, cpol and ncpha of the other chip select registers have no effect when the spi is programmed in slave mode. a npcs[0..3] write spi_tdr tdre npcs[0..3] write spi_tdr tdre npcs[0..3] write spi_tdr tdre dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs dlybct pcs=a a dlybcs dlybct a pcs = a a a dlybct aa csaat = 0 dlybct aa csaat = 1 a
240 at91sam7s64 preliminary 6070a?atarm?28-oct-04 the bits are shifted out on the miso line and sampled on the mosi line. when all the bits are processed, the received data is transferred in the receive data register and the rdrf bit rises. if rdrf is already high when the data is transferred, the overrun bit rises and the data transfer to spi_rdr is aborted. when a transfer starts, the data shifted out is the data present in the shift register. if no data has been written in the transmit data register (spi_tdr), the last data received is trans- ferred. if no data has been received since the last reset, all bits are transmitted low, as the shift register resets at 0. when a first data is written in spi_tdr, it is transferred immediately in the shift register and the tdre bit rises. if new data is written, it remains in spi_tdr until a transfer occurs, i.e. nss falls and there is a valid clock on the spck pin. when the transfer occurs, the last data written in spi_tdr is transferred in the shift register and the tdre bit rises. this enables frequent updates of critical variables with single transfers. then, a new data is loaded in the shift register from the transmit data register. in case no character is ready to be transmitted, i.e. no character has been written in spi_tdr since the last load from spi_tdr to the shift register, the shift register is not modified and the last received character is retransmitted. figure 89 shows a block diagram of the spi when operating in slave mode. figure 89. slave mode functional block diagram shift register spck spiens lsb msb nss mosi spi_rdr rd spi clock tdre spi_tdr td rdrf ovres spi_csr0 cpol ncpha bits fload spien spidis miso
241 at91sam7s64 preliminary 6070a?atarm?28-oct-04 serial peripheral interface (spi) user interface table 55. serial peripheral interface (spi) register mapping offset register register name access reset 0x00 control register spi_cr write-only --- 0x04 mode register spi_mr read/write 0x0 0x08 receive data register spi_rdr read-only 0x0 0x0c transmit data register spi_tdr write-only --- 0x10 status register spi_sr read-only 0x000000f0 0x14 interrupt enable register spi_ier write-only --- 0x18 interrupt disable register spi_idr write-only --- 0x1c interrupt mask register spi_imr read-only 0x0 0x20 - 0x2c reserved 0x30 chip select register 0 spi_csr0 read/write 0x0 0x34 chip select register 1 spi_csr1 read/write 0x0 0x38 chip select register 2 spi_csr2 read/write 0x0 0x3c chip select register 3 spi_csr3 read/write 0x0 0x004c - 0x00fc reserved ? ? ? 0x100 - 0x124 reserved for the pdc
242 at91sam7s64 preliminary 6070a?atarm?28-oct-04 spi control register name: spi_cr access type: write-only spien: spi enable 0 = no effect. 1 = enables the spi to transfer and receive data. spidis: spi disable 0 = no effect. 1 = disables the spi. all pins are set in input mode and no data is received or transmitted. if a transfer is in progress, the transfer is finished before the spi is disabled. if both spien and spidis are equal to one when the control register is written, the spi is disabled. swrst: spi software reset 0 = no effect. 1 = reset the spi. a software-triggered hardware reset of the spi interface is performed. lastxfer: last transfer 0 = no effect. 1 = the current npcs will be deasserted after the character written in td has been transferred. when csaat is set, this allows to close the communication with the current serial peripheral by raising the corresponding npcs line as soon as td transfer has completed. 31 30 29 28 27 26 25 24 ???????lastxfer 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst ? ? ? ? ? spidis spien
243 at91sam7s64 preliminary 6070a?atarm?28-oct-04 spi mode register name: spi_mr access type: read/write mstr: master/slave mode 0 = spi is in slave mode. 1 = spi is in master mode. ps: peripheral select 0 = fixed peripheral select. 1 = variable peripheral select. pcsdec: chip select decode 0 = the chip selects are directly connected to a peripheral device. 1 = the four chip select lines are connected to a 4- to 16-bit decoder. when pcsdec equals one, up to 15 chip select signals can be generated with the four lines using an external 4- to 16-bit decoder. the chip select registers define the characteristics of the 16 chip selects according to the following rules: spi_csr0 defines peripheral chip select signals 0 to 3. spi_csr1 defines peripheral chip select signals 4 to 7. spi_csr2 defines peripheral chip select signals 8 to 11. spi_csr3 defines peripheral chip select signals 12 to 15. fdiv: clock selection 0 = the spi operates at mck. 1 = the spi operates at mck/n. modfdis: mode fault detection 0 = mode fault detection is enabled. 1 = mode fault detection is disabled. llb: local loopback enable 0 = local loopback path disabled. 1 = local loopback path enabled. llb controls the local loopback on the data serializer for testing in master mode only. 31 30 29 28 27 26 25 24 dlybcs 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 ???????? 76543210 llb ? ? modfdis fdiv pcsdec ps mstr
244 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pcs: peripheral chip select this field is only used if fixed peripheral select is active (ps = 0). if pcsdec = 0: pcs = xxx0 npcs[3:0] = 1110 pcs = xx01 npcs[3:0] = 1101 pcs = x011 npcs[3:0] = 1011 pcs = 0111 npcs[3:0] = 0111 pcs = 1111 forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs. dlybcs: delay between chip selects this field defines the delay from npcs inactive to the activation of another npcs. the dlybcs time guarantees non-over- lapping chip selects and solves bus contentions in case of peripherals having long data float times. if dlybcs is less than or equal to six, six mck periods (or 6*n mck periods if fdiv is set) will be inserted by default. otherwise, the following equation determines the delay: if fdiv is 0: if fdiv is 1: delay between chip selects dlybcs mck ----------------------- = delay between chip selects dlybcs n mck --------------------------------- =
245 at91sam7s64 preliminary 6070a?atarm?28-oct-04 spi receive data register name: spi_rdr access type: read-only rd: receive data data received by the spi interface is stored in this register right-justified. unused bits read zero. pcs: peripheral chip select in master mode only, these bits indicate the value on the npcs pins at the end of a transfer. otherwise, these bits read zero. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 rd 76543210 rd
246 at91sam7s64 preliminary 6070a?atarm?28-oct-04 spi transmit data register name: spi_tdr access type: write-only td: transmit data data to be transmitted by the spi interface is stored in this register. information to be transmitted must be written to the transmit data register in a right-justified format. pcs: peripheral chip select this field is only used if variable peripheral select is active (ps = 1). if pcsdec = 0: pcs = xxx0 npcs[3:0] = 1110 pcs = xx01 npcs[3:0] = 1101 pcs = x011 npcs[3:0] = 1011 pcs = 0111 npcs[3:0] = 0111 pcs = 1111 forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs lastxfer: last transfer 0 = no effect. 1 = the current npcs will be deasserted after the character written in td has been transferred. when csaat is set, this allows to close the communication with the current serial peripheral by raising the corresponding npcs line as soon as td transfer has completed. 31 30 29 28 27 26 25 24 ???????lastxfer 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 td 76543210 td
247 at91sam7s64 preliminary 6070a?atarm?28-oct-04 spi status register name: spi_sr access type: read-only rdrf: receive data register full 0 = no data has been received since the last read of spi_rdr 1 = data has been received and the received data has been transferr ed from the serializer to spi_rdr since the last read of spi_rdr. tdre: transmit data register empty 0 = data has been written to spi_tdr and not yet transferred to the serializer. 1 = the last data written in the transmit data register has been transferred to the serializer. tdre equals zero when the spi is disabled or at reset. the spi enable command sets this bit to one. modf: mode fault error 0 = no mode fault has been detected since the last read of spi_sr. 1 = a mode fault occurred since the last read of the spi_sr. ovres: overrun error status 0 = no overrun has been detected since the last read of spi_sr. 1 = an overrun has occurred since the last read of spi_sr. an overrun occurs when spi_rdr is loaded at least twice from the serializer since the last read of the spi_rdr. endrx: end of rx buffer 0 = the receive counter register has not reache d 0 since the last write in spi_rcr or spi_rncr. 1 = the receive counter register has reached 0 since the last write in spi_rcr or spi_rncr. endtx: end of tx buffer 0 = the transmit counter register has not reached 0 since the last write in spi_tcr or spi_tncr. 1 = the transmit counter register has reached 0 since the last write in spi_tcr or spi_tncr. rxbuff: rx buffer full 0 = spi_rcr or spi_rncr has a value other than 0. 1 = both spi_rcr and spi_rncr has a value of 0. txbufe: tx buffer empty 0 = spi_tcr or spi_tncr has a value other than 0. 1 = both spi_tcr and spi_tncr has a value of 0. nssr: nss rising 0 = no rising edge detected on nss pin since last read. 1 = a rising edge occurred on nss pin since last read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????spiens 15 14 13 12 11 10 9 8 ??????txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
248 at91sam7s64 preliminary 6070a?atarm?28-oct-04 txempty: transmission registers empty 0 = as soon as data is written in spi_tdr. 1 = spi_tdr and internal shifter are empty. if a transfer delay has been defined, txempty is set after the completion of such delay. spiens: spi enable status 0 = spi is disabled. 1 = spi is enabled.
249 at91sam7s64 preliminary 6070a?atarm?28-oct-04 spi interrupt enable register name: spi_ier access type: write-only rdrf: receive data register full interrupt enable tdre: spi transmit data register empty interrupt enable modf: mode fault error interrupt enable ovres: overrun error interrupt enable endrx: end of receive buffer interrupt enable endtx: end of transmit buffer interrupt enable rxbuff: receive buffer full interrupt enable txbufe: transmit buffer empty interrupt enable txempty: transmission registers empty enable nssr: nss rising interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
250 at91sam7s64 preliminary 6070a?atarm?28-oct-04 spi interrupt disable register name: spi_idr access type: write-only rdrf: receive data register full interrupt disable tdre: spi transmit data register empty interrupt disable modf: mode fault error interrupt disable ovres: overrun error interrupt disable endrx: end of receive buffer interrupt disable endtx: end of transmit buffer interrupt disable rxbuff: receive buffer full interrupt disable txbufe: transmit buffer empty interrupt disable txempty: transmission registers empty disable nssr: nss rising interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
251 at91sam7s64 preliminary 6070a?atarm?28-oct-04 spi interrupt mask register name: spi_imr access type: read-only rdrf: receive data register full interrupt mask tdre: spi transmit data register empty interrupt mask modf: mode fault error interrupt mask ovres: overrun error interrupt mask endrx: end of receive buffer interrupt mask endtx: end of transmit buffer interrupt mask rxbuff: receive buffer full interrupt mask txbufe: transmit buffer empty interrupt mask txempty: transmission registers empty mask nssr: nss rising interrupt mask 0 = the corresponding interrupt is not enabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf
252 at91sam7s64 preliminary 6070a?atarm?28-oct-04 spi chip select register name: spi_csr0... spi_csr3 access type: read/write cpol: clock polarity 0 = the inactive state value of spck is logic level zero. 1 = the inactive state value of spck is logic level one. cpol is used to determine the inactive state value of the serial clock (spck). it is used with ncpha to produce the required clock/data relationship between master and slave devices. ncpha: clock phase 0 = data is changed on the leading edge of spck and captured on the following edge of spck. 1 = data is captured on the leading edge of spck and changed on the following edge of spck. ncpha determines which edge of spck causes data to change and which edge causes data to be captured. ncpha is used with cpol to produce the required clock/data relationship between master and slave devices. csaat: chip select active after transfer 0 = the peripheral chip select line rises as soon as the last transfer is achieved. 1 = the peripheral chip select does not rise after the last transfer is achieved. it remains active until a new transfer is requested on a different chip select. bits: bits per transfer the bits field determines the number of data bits transferred. reserved values should not be used. 31 30 29 28 27 26 25 24 dlybct 23 22 21 20 19 18 17 16 dlybs 15 14 13 12 11 10 9 8 scbr 76543210 bits csaat ? ncpha cpol bits bits per transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved
253 at91sam7s64 preliminary 6070a?atarm?28-oct-04 scbr: serial clock baud rate in master mode, the spi interface uses a modulus counter to derive the spck baud rate from the master clock mck. the baud rate is selected by writing a value from 1 to 255 in the scbr field. the following equations determine the spck baud rate: if fdiv is 0: if fdiv is 1: note: n = 32 programming the scbr field at 0 is forbidden. triggering a transfer while scbr is at 0 can lead to unpredictable results. at reset, scbr is 0 and the user has to program it at a valid value before performing the first transfer. dlybs: delay before spck this field defines the delay from npcs valid to the first valid spck transition. when dlybs equals zero, the npcs valid to spck transition is 1/2 the spck clock period. otherwise, the following equations determine the delay: if fdiv is 0: if fdiv is 1: note: n = 32 dlybct: delay between consecutive transfers this field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. the delay is always inserted after each transfer and before removing the chip select if needed. when dlybct equals zero, no delay between consecutive transfers is inserted and th e clock keeps its duty cycle over the character transfers. otherwise, the following equation determines the delay: if fdiv is 0: if fdiv is 1: note: n = 32 spck baudrate mck scbr -------------- - = spck baudrate mck nscbr () ------------------------------ = delay before spck dlybs mck ------------------ - = delay before spck ndlybs mck ---------------------------- - = delay between consecutive transfers 32 dlybct mck ------------------------------------ scbr 2 mck ---------------- - + = delay between consecutive transfers 32 n dlybct mck ---------------------------------------------- - nscbr 2 mck ------------------------- + =
254 at91sam7s64 preliminary 6070a?atarm?28-oct-04
255 at91sam7s64 preliminary 6070a?atarm?28-oct-04 two-wire interface (twi) overview the two-wire interface (twi) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbits per second, based on a byte- oriented transfer format. it can be used with any atmel two-wire bus serial eeprom. the twi is programmable as a master with sequential or single-byte access. a configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. block diagram figure 90. block diagram application block diagram figure 91. application block diagram apb bridge pmc mck two-wire interface pio aic twi interrupt twck twd host with twi interface twd twck at24lc16 u1 at24lc16 u2 lcd controller u3 slave 1 slave 2 slave 3 rr vdd
256 at91sam7s64 preliminary 6070a?atarm?28-oct-04 product dependencies i/o lines description both twd and twck are bidirectional lines, connected to a positive supply voltage via a cur- rent source or pull-up resistor (see figure 91 on page 255). when the bus is free, both lines are high. the output stages of devices connected to the bus must have an open-drain or open- collector to perform the wired-and function. twd and twck pins may be multiplexed with pio lines. to enable the twi, the programmer must perform the following steps: program the pio controller to: ? dedicate twd and twck as peripheral lines. ? define twd and twck as open-drain. power management enable the peripheral clock. the twi interface may be clocked through the power management controller (pmc), thus the programmer must first configure the pmc to enable the twi clock. interrupt the twi interface has an interrupt line connected to the advanced interrupt controller (aic). in order to handle interrupts, the aic must be programmed before configuring the twi. table 56. i/o lines description pin name pin description type twd two-wire serial data input/output twck two-wire serial clock input/output
257 at91sam7s64 preliminary 6070a?atarm?28-oct-04 functional description transfer format the data put on the twd line must be 8 bits long. data is transferred msb first; each byte must be followed by an acknowledgement. the number of bytes per transfer is unlimited (see figure 93 on page 257). each transfer begins with a start condition and terminates with a stop condition (see fig- ure 92 on page 257). a high-to-low transition on the twd line while twck is high defines the start condition. a low-to-high transition on the twd line while twck is high defines a stop condition. figure 92. start and stop conditions figure 93. transfer format modes of operation the twi has two modes of operation: master transmitter mode master receiver mode the twi control register (twi_cr) allows configuration of the interface in master mode. in this mode, it generates the clock according to the value programmed in the clock waveform generator register (twi_cwgr). this register defines the twck signal completely, enabling the interface to be adapted to a wide range of clocks. transmitting data after the master initiates a start condition, it sends a 7-bit slave address, configured in the master mode register (dadr in twi_mmr), to notify the slave device. the bit following the slave address indicates the transfer direction (write or read). if this bit is 0, it indicates a write operation (transmit operation). if the bit is 1, it indicates a request for data read (receive operation). the twi transfers require the slave to acknowledge each received byte. during the acknowl- edge clock pulse, the master releases the data line (high), enabling the slave to pull it down in order to generate the acknowledge. the master polls the data line during this clock pulse and sets the nak bit in the status register if the slave does not acknowledge the byte. as with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (twi_ier). after writing in the transmit-holding register (twi_thr), setting the start bit in twd twck start stop twd twck start address r/w ack data ack data ack stop
258 at91sam7s64 preliminary 6070a?atarm?28-oct-04 the control register starts the transmission. the data is shifted in the internal shifter and when an acknowledge is detected, the txrdy bit is set until a new write in the twi_thr (see fig- ure 95 below). the master generates a stop condition to end the transfer. the read sequence begins by setting the start bit. when the rxrdy bit is set in the status register, a character has been received in the receive-holding register (twi_rhr). the rxrdy bit is reset when reading the twi_rhr. the twi interface performs various transfer formats (7-bit slave address, 10-bit slave address). the three internal address bytes are configurable through the master mode register (twi_mmr). if the slave device supports only a 7-bit address, iadrsz must be set to 0. for a slave address higher than 7 bits, the user must configure the address size (iadrsz ) and set the other slave address bits in the internal address register (twi_iadr). figure 94. master write with one, two or three bytes internal address and one data byte figure 95. master write with one byte internal address and multiple data bytes figure 96. master read with one, two or three bytes internal address and one data byte s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a data ap s dadr w a iadr(15:8) a iadr(7:0) a p data a a iadr(7:0) a p data a s dadr w twd three bytes internal address two bytes internal address one byte internal address twd twd a iadr(7:0) a data a s dadr w data a p data a txcomp txrdy write thr write thr write thr write thr twd s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a s dadr w a iadr(15:8) a iadr(7:0) a a iadr(7:0) a s dadr w data n p s dadr r a s dadr r a data n p s dadr r a data n p twd twd twd three bytes internal address two bytes internal address one byte internal address
259 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 97. master read with one byte internal address and multiple data bytes s = start p = stop w = write/read a = acknowledge dadr= device address iadr = internal address figure 98 below shows a byte write to an atmel at24lc512 eeprom. this demonstrates the use of internal addresses to access the device. figure 98. internal address usage a iadr(7:0) a s dadr w s dadr r a data a data n p txcomp write start bit rxrdy write stop bit read rhr read rhr twd s t a r t m s b device address 0 l s b r / w a c k m s b w r i t e a c k a c k l s b a c k first word address second word address data s t o p
260 at91sam7s64 preliminary 6070a?atarm?28-oct-04 read/write flowcharts the following flowcharts shown in figure 99 on page 260 and in figure 100 on page 261 give examples for read and write operations in master mode. a polling or interrupt method can be used to check the status bits. the interrupt method requires that the interrupt enable register (twi_ier) be configured first. figure 99. twi write in master mode set twi clock: twi_cwgr = clock set the control register: - master enable twi_cr = msen set the master mode register: - device slave address - internal address size - transfer direction bit write ==> bit mread = 0 internal address size = 0? load transmit register twi_thr = data to send start the transfer twi_cr = start stop the transfer twi_cr = stop read status register txrdy = 0? data to send? read status register txcomp = 0? end start set theinternal address twi_iadr = address ye s twi_thr = data to send ye s ye s ye s
261 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 100. twi read in master mode set twi clock: twi_cwgr = clock set the control register: - master enable - slave disable twi_cr = msen set the master mode register: - device slave address - internal address size - transfer direction bit read ==> bit mread = 0 internal address size = 0? start the transfer twi_cr = start stop the transfer twi_cr = stop read status register rxrdy = 0? data to read? read status register txcomp = 0? end start set the internal address twi_iadr = address ye s ye s ye s ye s
262 at91sam7s64 preliminary 6070a?atarm?28-oct-04 two-wire interface (twi) user interface table 57. two-wire interface (twi) register mapping offset register name access reset value 0x0000 control register twi_cr write-only n/a 0x0004 master mode register twi_mmr read/write 0x0000 0x0008 reserved ? ? ? 0x000c internal address register twi_iadr read/write 0x0000 0x0010 clock waveform generator register twi_cwgr read/write 0x0000 0x0020 status register twi_sr read-only 0x0008 0x0024 interrupt enable register twi_ier write-only n/a 0x0028 interrupt disable register twi_idr write-only n/a 0x002c interrupt mask register twi_imr read-only 0x0000 0x0030 receive holding register twi_rhr read-only 0x0000 0x0034 transmit holding register twi_thr read/write 0x0000 0x0038-0x00fc reserved ? ? ?
263 at91sam7s64 preliminary 6070a?atarm?28-oct-04 twi control register register name :twi_cr access type : write-only start: send a start condition 0 = no effect. 1 = a frame beginning with a start bit is transmitted according to the features defined in the mode register. this action is necessary when the twi peripheral wants to read data from a slave. when configured in master mode with a write operation, a frame is sent with the mode register as soon as the user writes a character in the holding register. stop: send a stop condition 0 = no effect. 1 = stop condition is sent just after completing the current byte transmission in master read or write mode. in single data byte master read or write, the start and stop must both be set. in multiple data bytes master read or write, the stop must be set before ack/nack bit transmission. in master read mode, if a nack bit is received, the stop is automatically performed. in multiple data write operation, when both thr and shift register are empty, a stop condition is automatically sent. msen: twi master transfer enabled 0 = no effect. 1 = if msdis = 0, the master data transfer is enabled. msdis: twi master transfer disabled 0 = no effect. 1 = the master data transfer is disabled, all pending data is transmitted. the shifter and holding characters (if they contain data) are transmitted in case of write operation. in read operation, the character being transferred must be completely received before disabling. swrst: software reset 0 = no effect. 1 = equivalent to a system reset. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst ? ? ? msdis msen stop start
264 at91sam7s64 preliminary 6070a?atarm?28-oct-04 twi master mode register register name :twi_mmr address type : read/write iadrsz: internal device address size mread: master read direction 0 = master write direction. 1 = master read direction. dadr: device address the device address is used in master mode to access slave devices in read or write mode. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?dadr 15 14 13 12 11 10 9 8 ???mread?? iadrsz 76543210 ???????? iadrsz[9:8] 00 no internal device address 01 one-byte internal device address 10 two-byte internal device address 11 three-byte internal device address
265 at91sam7s64 preliminary 6070a?atarm?28-oct-04 twi internal address register register name :twi_iadr access type : read/write iadr: internal address 0, 1, 2 or 3 bytes depending on iadrsz. twi clock waveform generator register register name : twi_cwgr access type : read/write cldiv: clock low divider the scl low period is defined as follows: chdiv: clock high divider the scl high period is defined as follows: ckdiv: clock divider the ckdiv is used to increase both scl high and low periods. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 iadr 15 14 13 12 11 10 9 8 iadr 76543210 iadr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????? ckdiv 15 14 13 12 11 10 9 8 chdiv 76543210 cldiv t low cldiv ( 2 ckdiv () 3 ) + t mck = t high chdiv ( 2 ckdiv () 3 ) + t mck =
266 at91sam7s64 preliminary 6070a?atarm?28-oct-04 twi status register register name :twi_sr access type : read-only txcomp: transmission completed 0 = in master, during the length of the current frame. in slave, from start received to stop received. 1 = when both holding and shift registers are empty and stop condition has been sent (in master) or received (in slave), or when msen is set (enable twi). rxrdy: receive holding register ready 0 = no character has been received since the last twi_rhr read operation. 1 = a byte has been received in the twi_rhr since the last read. txrdy: transmit holding register ready 0 = the transmit holding register has not been transferred into shift register. set to 0 when writing into twi_thr register. 1 = as soon as data byte is transferred from twi_thr to internal shifter or if a nack error is detected, txrdy is set at the same time as txcomp and nack. txrdy is also set when msen is set (enable twi). ovre: overrun error 0 = twi_rhr has not been loaded while rxrdy was set 1 = twi_rhr has been loaded while rxrdy was set. reset by read in twi_sr when txcomp is set. unre: underrun error 0 = no underrun error 1 = no valid data in twi_thr (txrdy set) while trying to load the data shifter. this action automatically generated a stop bit in master mode. reset by read in twi_sr when txcomp is set. nack: not acknowledged 0 = each data byte has been correctly received by the far-end side twi slave component. 1 = a data byte has not been acknowledged by the slave component. set at the same time as txcomp. reset after read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????nack 76543210 unre ovre ? ? ? txrdy rxrdy txcomp
267 at91sam7s64 preliminary 6070a?atarm?28-oct-04 twi interrupt enable register register name :twi_ier access type : write-only txcomp: transmission completed rxrdy: receive holding register ready txrdy: transmit holding register ready ovre: overrun error unre: underrun error nack: not acknowledge 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????nack 76543210 unre ovre ? ? ? txrdy rxrdy txcomp
268 at91sam7s64 preliminary 6070a?atarm?28-oct-04 twi interrupt disable register register name :twi_idr access type : write-only txcomp: transmission completed rxrdy: receive holding register ready txrdy: transmit holding register ready ovre: overrun error unre: underrun error nack: not acknowledge 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????nack 76543210 unre ovre ? ? ? txrdy rxrdy txcomp
269 at91sam7s64 preliminary 6070a?atarm?28-oct-04 twi interrupt mask register register name :twi_imr access type : read-only txcomp: transmission completed rxrdy: receive holding register ready txrdy: transmit holding register ready ovre: overrun error unre: underrun error nack: not acknowledge 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????nack 76543210 unre ovre ? ? ? txrdy rxrdy txcomp
270 at91sam7s64 preliminary 6070a?atarm?28-oct-04 twi receive holding register register name : twi_rhr access type : read-only rxdata: master or slave receive holding data twi transmit holding register register name :twi_thr access type : read/write txdata: master or slave transmit holding data 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rxdata 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 txdata
271 at91sam7s64 preliminary 6070a?atarm?28-oct-04 universal synchronous/asynchronous receiver/transmitter (usart) overview the universal synchronous asynchronous receiver transceiver (usart) provides one full duplex universal synchronous asynchronous serial link. data frame format is widely program- mable (data length, parity, number of stop bits) to support a maximum of standards. the receiver implements parity error, framing error and overrun error detection. the receiver time- out enables handling variable-length frames and the transmitter timeguard facilitates commu- nications with slow remote devices. multi-drop communications are also supported through address bit handling in reception and transmission. the usart features three test modes: remote loopback, local loopback and automatic echo. the usart supports specific operating modes providing interfaces on rs485 buses, with iso7816 t = 0 or t = 1 smart card slots, infrared transceivers and connection to modem ports. the hardware handshaking feature enables an out-of-band flow control by automatic manage- ment of the pins rts and cts. the usart supports the connection to the peripheral data controller, which enables data transfers to the transmitter and from the receiver. the pdc provides chained buffer manage- ment without any intervention of the processor.
272 at91sam7s64 preliminary 6070a?atarm?28-oct-04 block diagram figure 101. usart block diagram peripheral data controller channel channel aic receiver usart interrupt rxd txd sck usart pio controller cts rts dtr dsr dcd ri transmitter modem signals control baud rate generator user interface pmc mck slck div mck/div apb
273 at91sam7s64 preliminary 6070a?atarm?28-oct-04 application block diagram figure 102. application block diagram i/o lines description smart card slot usart rs232 drivers modem rs485 drivers differential bus irda transceivers modem driver field bus driver emv driver irda driver irlap rs232 drivers serial port serial driver ppp pstn table 58. i/o line description name description type active level sck serial clock i/o txd transmit serial data i/o rxd receive serial data input ri ring indicator input low dsr data set ready input low dcd data carrier detect input low dtr data terminal ready output low cts clear to send input low rts request to send output low
274 at91sam7s64 preliminary 6070a?atarm?28-oct-04 product dependencies i/o lines the pins used for interfacing the usart may be multiplexed with the pio lines. the program- mer must first program the pio controller to assign the desired usart pins to their peripheral function. if i/o lines of the usart are not used by the application, they can be used for other purposes by the pio controller. all the pins of the modems may or may not not be implemented on the usart within a prod- uct. frequently, only the usart1 is fully equipped with all the modem signals. for the other usarts of the product not equipped with the corresponding pin, the associated control bits and statuses have no effect on the behavior of the usart. power management the usart is not continuously clocked. the programmer must first enable the usart clock in the power management controller (pmc) before using the usart. however, if the applica- tion does not require usart operations, the usart clock can be stopped when not needed and be restarted later. in this case, the usart will resume its operations where it left off. configuring the usart does not require the usart clock to be enabled. interrupt the usart interrupt line is connected on one of the internal sources of the advanced inter- rupt controller. using the usart interrupt requires the aic to be programmed first. note that it is not recommended to use the usart interrupt line in edge sensitive mode.
275 at91sam7s64 preliminary 6070a?atarm?28-oct-04 functional description the usart is capable of managing several types of serial synchronous or asynchronous communications. it supports the following communication modes: 5- to 9-bit full-duplex asynchronous serial communication ? msb- or lsb-first ? 1, 1.5 or 2 stop bits ? parity even, odd, marked, space or none ? by 8 or by 16 over-sampling receiver frequency ? optional hardware handshaking ? optional modem signals management ? optional break management ? optional multi-drop serial communication high-speed 5- to 9-bit full-duplex synchronous serial communication ? msb- or lsb-first ? 1 or 2 stop bits ? parity even, odd, marked, space or none ? by 8 or by 16 over-sampling frequency ? optional hardware handshaking ? optional modem signals management ? optional break management ? optional multi-drop serial communication rs485 with driver control signal iso7816, t0 or t1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit infrared irda modulation and demodulation test modes ? remote loopback, local loopback, automatic echo baud rate generator the baud rate generator provides the bit period clock named the baud rate clock to both the receiver and the transmitter. the baud rate generator clock source can be selected by setting the usclks field in the mode register (us_mr) between: the master clock mck a division of the master clock, the divider being product dependent, but generally set to 8 the external clock, available on the sck pin the baud rate generator is based upon a 16-bit divider, which is programmed with the cd field of the baud rate generator register (us_brgr). if cd is programmed at 0, the baud rate generator does not generate any clock. if cd is programmed at 1, the divider is bypassed and becomes inactive. if the external sck clock is selected, the duration of the low and high levels of the signal pro- vided on the sck pin must be longer than a master clock (mck) period. the frequency of the signal provided on sck must be at least 4.5 times lower than mck.
276 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 103. baud rate generator baud rate in asynchronous mode if the usart is programmed to operate in asynchronous mode, the selected clock is first divided by cd, which is field programmed in the baud rate generator register (us_brgr). the resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the over bit in us_mr. if over is set to 1, the receiver sampling is 8 times higher than the baud rate clock. if over is cleared, the sampling is performed at 16 times the baud rate clock. the following formula performs the calculation of the baud rate. this gives a maximum baud rate of mck divided by 8, assuming that mck is the highest pos- sible clock and that over is programmed at 1. baud rate calculation example table 59 shows calculations of cd to obtain a baud rate at 38400 bauds for different source clock frequencies. this table also shows the actual resulting baud rate and the error. mck/div 16-bit counter 0 baud rate clock cd cd sampling divider 0 1 >1 sampling clock reserved mck sck usclks over sck sync sync usclks = 3 1 0 2 3 0 1 0 1 fidi baudrate selectedclock 82 over ? () cd () -------------------------------------------- = table 59. baud rate example (over = 0) source clock expected baud rate calculation result cd actual baud rate error mhz bit/s bit/s 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.02 13 38 461.54 0.16% 12 000 000 38 400 19.53 20 37 500.00 2.40% 12 288 000 38 400 20.00 20 38 400.00 0.00% 14 318 180 38 400 23.30 23 38 908.10 1.31% 14 745 600 38 400 24.00 24 38 400.00 0.00%
277 at91sam7s64 preliminary 6070a?atarm?28-oct-04 the baud rate is calculated with the following formula: the baud rate error is calculated with the following formula. it is not recommended to work with an error higher than 5%. baud rate in synchronous mode if the usart is programmed to operate in synchronous mode, the selected clock is simply divided by the field cd in us_brgr. in synchronous mode, if the external clock is selected (usclks = 3), the clock is provided directly by the signal on the usart sck pin. no division is active. the value written in us_brgr has no effect. the external clock frequency must be at least 4.5 times lower than the system clock. when either the external clock sck or the internal clock divided (mck/div) is selected, the value programmed in cd must be even if the user has to ensure a 50:50 mark/space ratio on the sck pin. if the internal clock mck is selected, the baud rate generator ensures a 50:50 duty cycle on the sck pin, even if the value programmed in cd is odd. baud rate in iso 7816 mode the iso7816 specification defines the bit rate with the following formula: where: b is the bit rate di is the bit-rate adjustment factor fi is the clock frequency division factor f is the iso7816 clock frequency (hz) 18 432 000 38 400 30.00 30 38 400.00 0.00% 24 000 000 38 400 39.06 39 38 461.54 0.16% 24 576 000 38 400 40.00 40 38 400.00 0.00% 25 000 000 38 400 40.69 40 38 109.76 0.76% 32 000 000 38 400 52.08 52 38 461.54 0.16% 32 768 000 38 400 53.33 53 38 641.51 0.63% 33 000 000 38 400 53.71 54 38 194.44 0.54% 40 000 000 38 400 65.10 65 38 461.54 0.16% 50 000 000 38 400 81.38 81 38 580.25 0.47% 60 000 000 38 400 97.66 98 38 265.31 0.35% 70 000 000 38 400 113.93 114 38 377.19 0.06% table 59. baud rate example (over = 0) (continued) source clock expected baud rate calculation result cd actual baud rate error baudrate mck cd 16 ? = error 1 expectedbaudrate actualbaudrate -------------------------------------------------- - ?? ?? ? = baudrate selectedclock cd ------------------------------------- - = b di fi ----- - f =
278 at91sam7s64 preliminary 6070a?atarm?28-oct-04 di is a binary value encoded on a 4-bit field, named di, as represented in table 60. fi is a binary value encoded on a 4-bit field, named fi, as represented in table 61. table 62 shows the resulting fi/di ratio, which is the ratio between the iso7816 clock and the baud rate clock. if the usart is configured in iso7816 mode, the clock selected by the usclks field in the mode register (us_mr) is first divided by the value programmed in the field cd in the baud rate generator register (us_brgr). the resulting clock can be provided to the sck pin to feed the smart card clock inputs. this means that the clko bit can be set in us_mr. this clock is then divided by the value programmed in the fi_di_ratio field in the fi_di_ratio register (us_fidi). this is performed by the sampling divider, which performs a division by up to 2047 in iso7816 mode. the non-integer values of the fi/di ratio are not sup- ported and the user must program the fi_di_ratio field to a value as close as possible to the expected value. the fi_di_ratio field resets to the value 0x174 (372 in decimal) and is the most common divider between the iso7816 clock and the bit rate (fi = 372, di = 1). figure 104 shows the relation between the elementary time unit, corresponding to a bit time, and the iso 7816 clock. table 60. binary and decimal values for d di field 0001 0010 0011 0100 0101 0110 1000 1001 di (decimal) 1 2 4 8 16 32 12 20 table 61. binary and decimal values for f fi field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 fi (decimal 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 table 62. possible values for the fi/di ratio fi/di 372 558 774 1116 1488 1806 512 768 1024 1536 2048 1 372 558 744 1116 1488 1860 512 768 1024 1536 2048 2 186 279 372 558 744 930 256 384 512 768 1024 4 93 139.5 186 279 372 465 128 192 256 384 512 8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256 16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128 32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64 12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6 20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4
279 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 104. elementary time unit (etu) receiver and transmitter control after reset, the receiver is disabled. the user must enable the receiver by setting the rxen bit in the control register (us_cr). however, the receiver registers can be programmed before the receiver clock is enabled. after reset, the transmitter is disabled. the user must enable it by setting the txen bit in the control register (us_cr). however, the tr ansmitter registers can be programmed before being enabled. the receiver and the transmitter can be enabled together or independently. at any time, the software can perform a reset on the receiver or the transmitter of the usart by setting the corresponding bit, rstrx and rsttx respectively, in the control register (us_cr). the reset commands have the same effect as a hardware reset on the correspond- ing logic. regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. the user can also independently disable the receiver or the transmitter by setting rxdis and txdis respectively in us_cr. if the receiver is disabled during a character reception, the usart waits until the end of reception of the current character, then the reception is stopped. if the transmitter is disabled while it is operating, the usart waits the end of transmission of both the current character and character being stored in the transmit holding register (us_thr). if a timeguard is programmed, it is handled normally. synchronous and asynchronous modes transmitter operations the transmitter performs the same in both synchronous and asynchronous operating modes (sync = 0 or sync = 1). one start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the txd pin at each falling edge of the programmed serial clock. the number of data bits is selected by the chrl field and the mode9 bit in the mode regis- ter (us_mr). nine bits are selected by setting the mode 9 bit regardless of the chrl field. the parity bit is set according to the par field in us_mr. the even, odd, space, marked or none parity bit can be configured. the msbf field in us_mr configures which data bit is sent first. if written at 1, the most significant bit is sent first. at 0, the less significant bit is sent first. the number of stop bits is selected by the nbstop field in us_mr. the 1.5 stop bit is sup- ported in asynchronous mode only. 1 etu iso7816 clock on sck iso7816 i/o line on txd fi_di_ratio iso7816 clock cycles
280 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 105. character transmit the characters are sent by writing in the transmit holding register (us_thr). the transmit- ter reports two status bits in the channel status register (us_csr): txrdy (transmitter ready), which indicates that us_thr is empty and txempty, which indicates that all the characters written in us_thr have been processed. when the current character processing is completed, the last character written in us_thr is transferred into the shift register of the transmitter and us_thr becomes empty, thus txrdy raises. both txrdy and txempty bits are low since the transmitter is disabled. writing a character in us_thr while txrdy is active has no effect and the written character is lost. figure 106. transmitter status asynchronous receiver if the usart is programmed in asynchronous operating mode (sync = 0), the receiver over- samples the rxd input line. the oversampling is either 16 or 8 times the baud rate clock, depending on the over bit in the mode register (us_mr). the receiver samples the rxd line. if the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. if the oversampling is 16, (over at 0), a start is detected at the eighth sample at 0. then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. if the oversampling is 8 (over at 1), a start bit is detected at the fourth sample at 0. then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. the number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively chrl, mode9, msbf and par. the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field nbstop, so that resynchronization between the receiver and the transmitter can occur. moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchro- nization can also be accomplished when the transmitter is operating with one stop bit. d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit example: 8-bit, parity enabled one stop baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty
281 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 107 and figure 108 illustrate start detection and character reception when usart operates in asynchronous mode. figure 107. asynchronous start detection figure 108. asynchronous character reception sampling clock (x16) rxd start detection sampling baud rate clock rxd start rejection sampling 12345678 12345670 1234 12345678 9 10111213141516 d0 sampling d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit stop bit example: 8-bit, parity enabled baud rate clock start detection 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples
282 at91sam7s64 preliminary 6070a?atarm?28-oct-04 synchronous receiver in synchronous mode (sync = 1), the receiver samples the rxd signal on each rising edge of the baud rate clock. if a low level is detected, it is considered as a start. all data bits, the par- ity bit and the stop bits are sampled and the receiver waits for the next start bit. synchronous mode operations provide a high speed transfer capability. configuration fields and bits are the same as in asynchronous mode. figure 109 illustrates a character reception in synchronous mode. figure 109. synchronous mode character reception receiver operations when a character reception is completed, it is transferred to the receive holding register (us_rhr) and the rxrdy bit in the status register (us_csr) rises. if a character is com- pleted while the rxrdy is set, the ovre (overrun error) bit is set. the last character is transferred into us_rhr and overwrites the prev ious one. the ovre bit is cleared by writing the control register (us_cr) with the rststa (reset status) bit at 1. figure 110. receiver status d0 d1 d2 d3 d4 d5 d6 d7 rxd start sampling parity bit stop bit example: 8-bit, parity enabled 1 stop baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr rxrdy ovre d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit rststa = 1 read us_rhr
283 at91sam7s64 preliminary 6070a?atarm?28-oct-04 parity the usart supports five parity modes selected by programming the par field in the mode register (us_mr). the par field also enables the multidrop mode, which is discussed in a separate paragraph. even and odd parity bit generation and error detection are supported. if even parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. if the odd parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd. accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. if the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. the receiver parity checker reports an error if the parity bit is sampled at 0.if the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. the receiver parity checker reports an error if the parity bit is sampled at 1. if parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. table 63 shows an example of the parity bit for the character 0x41 (character ascii ?a?) depending on the configuration of the usart. because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. i when the receiver detects a parity error, it sets the pare (parity error) bit in the channel sta- tus register (us_csr). the pare bit can be cl eared by writing the control register (us_cr) with the rststa bit at 1. fi gure 111 illustrates the parity bit st atus setting and clearing. figure 111. parity error table 63. parity bit examples character hexa binary parity bit parity mode a 0x41 0100 0001 1 odd a 0x41 0100 0001 0 even a 0x41 0100 0001 1 mark a 0x41 0100 0001 0 space a 0x41 0100 0001 none none d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit bad parity bit stop bit baud rate clock write us_cr pare rxrdy rststa = 1
284 at91sam7s64 preliminary 6070a?atarm?28-oct-04 multi-drop mode if the par field in the mode register (us_mr) is programmed to the value 0x6 or 0x7, the usart runs in multi-drop mode. this mode differentiates the data characters and the address characters. data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. if the usart is configured in multi-drop mode, the receiver sets the pare parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the control register is written with the senda bit at 1. to handle parity error, the pare bit is cleared when the control register is written with the bit rststa at 1. the transmitter sends an address byte (parity bit set) when senda is written to us_cr. in this case, the next byte written to us_thr is transmitted as an address. any character written in us_thr without having written the command senda is transmitted normally with the parity at 0. transmitter timeguard the timeguard feature enables the usart interface with slow remote devices. the timeguard function enables the transmitter to insert an idle state on the txd line between two characters. this idle state actually acts as a long stop bit. the duration of the idle state is programmed in the tg field of the transmitter timeguard reg- ister (us_ttgr). when this field is programmed at zero no timeguard is generated. otherwise, the transmitter holds a high level on txd after each transmitted byte during the number of bit periods programmed in tg in addition to the number of stop bits. as illustrated in figure 112, the behavior of txrdy and txempty status bits is modified by the programming of a timeguard. txrdy rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in us_thr. txempty remains low until the timeguard transmission is completed as the time- guard is part of the current character being transmitted. figure 112. timeguard operations d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit tg = 4 write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty tg = 4
285 at91sam7s64 preliminary 6070a?atarm?28-oct-04 table 64 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the baud rate. receiver time-out the receiver time-out provides support in handling variable-length frames. this feature detects an idle condition on the rxd line. when a time-out is detected, the bit timeout in the channel status register (us_csr) rises and can generate an interrupt, thus indicating to the driver an end of frame. the time-out delay period (during which the receiver waits for a new character) is programmed in the to field of the receiver time-out register (us_rtor). if the to field is programmed at 0, the receiver time-out is disabled and no time-out is detected. the timeout bit in us_csr remains at 0. otherwise, the receiver loads a 16-bit counter with the value pro- grammed in to. this counter is decremented at each bit period and reloaded each time a new character is received. if the counter reaches 0, the timeout bit in the status register rises. the user can either: obtain an interrupt when a time-out is detected after having received at least one character. this is performed by writing the control register (us_cr) with the sttto (start time-out) bit at 1. obtain a periodic interrupt while no character is received. this is performed by writing us_cr with the retto (reload and start time-out) bit at 1. if sttto is performed, the counter clock is stopped until a first character is received. the idle state on rxd before the start of the frame does not provide a time-out. this prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on rxd is detected. if retto is performed, the counter starts counting down immediately from the value to. this enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. figure 113 shows the block diagram of the receiver time-out feature. table 64. maximum timeguard length depending on baud rate baud rate bit time timeguard bit/sec s ms 1 200 833 212.50 9 600 104 26.56 14400 69.4 17.71 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21
286 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 113. receiver time-out block diagram table 65 gives the maximum time-out period for some standard baud rates.t framing error the receiver is capable of detecting framing errors. a framing error happens when the stop bit of a received character is detected at level 0. this can occur if the receiver and the transmitter are fully desynchronized. a framing error is reported on the frame bit of the channel status register (us_csr). the frame bit is asserted in the middle of the stop bit as soon as the framing error is detected. it is cleared by writing the control register (us_cr) with the rststa bit at 1. table 65. maximum time-out period baud rate bit time time-out bit/sec s ms 600 1 667 109 225 1 200 833 54 613 2 400 417 27 306 4 800 208 13 653 9 600 104 6 827 14400 69 4 551 19200 52 3 413 28800 35 2 276 33400 30 1 962 56000 18 1 170 57600 17 1 138 200000 5 328 16-bit time-out counter 0 to timeout baud rate clock = character received retto load clock 16-bit value sttto dq 1 clear
287 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 114. framing error status transmit break the user can request the transmitter to generate a break condition on the txd line. a break condition drives the txd line low during at least one complete character. it appears the same as a 0x00 character sent with the parity and the stop bits at 0. however, the transmitter holds the txd line at least during one character until the user requests the break condition to be removed. a break is transmitted by writing the control register (us_cr) with the sttbrk bit at 1. this can be performed at any time, either while the transmitter is empty (no character in either the shift register or in us_thr) or when a characte r is being transmitted. if a break is requested while a character is being shifted out, the character is first completed before the txd line is held low. once sttbrk command is requested further sttbrk commands are ignored until the end of the break is completed. the break condition is removed by writing us_cr with the stpbrk bit at 1. if the stpbrk is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. the transmitter considers the break as though it is a character, i.e. the sttbrk and stpbrk commands are taken into account only if the txrdy bit in us_csr is at 1 and the start of the break condition clears the txrdy and txempty bits as if a character is processed. writing us_cr with the both sttbrk and stpbrk bits at 1 can lead to an unpredictable result. all stpbrk commands requested without a previous sttbrk command are ignored. a byte written into the transmit holding register while a break is pending, but not started, is ignored. after the break condition, the transmitter returns the txd line to 1 for a minimum of 12 bit times. thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. if the timeguard is programmed with a value higher than 12, the txd line is held high for the timeguard period. after holding the txd line for this period, the transmitter resumes normal operations. figure 115 illustrates the effect of both the start break (sttbrk) and stop break (stp brk) commands on the txd line. d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr frame rxrdy rststa = 1
288 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 115. break transmission receive break the receiver detects a break condition when all data, parity and stop bits are low. this corre- sponds to detecting a framing error with data at 0x00, but frame remains low. when the low stop bit is detected, the receiver asserts the rxbrk bit in us_csr. this bit may be cleared by writing the control register (us_cr) with the bit rststa at 1. an end of receive break is detected by a high level for at least 2/16 of a bit period in asynchro- nous operating mode or one sample at high level in synchronous operating mode. the end of break detection also asserts the rxbrk bit. hardware handshaking the usart features a hardware handshaking out-of-band flow control. the rts and cts pins are used to connect with the remote device, as shown in figure 116. figure 116. connection with a remote device for hardware handshaking setting the usart to operate with hardware handshaking is performed by writing the usart_mode field in the mode register (us_mr) to the value 0x2. the usart behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the rts pin as described below and the level on the cts pin modifies the behavior of the transmitter as described below. using this mode requires using the pdc channel for reception. the transmit- ter can handle hardware handshaking in any case. figure 117 shows how the receiver operates if hardware handshaking is enabled. the rts pin is driven high if the receiver is disabled and if the status rxbuff (receive buffer full) coming from the pdc channel is high. normally, the remote device does not start transmitting while its cts pin (driven by rts) is high. as soon as the receiver is enabled, the rts falls, indicating to the remote device that it can start transmitting. defining a new buffer to the pdc clears the status bit rxbuff and, as a result, asserts the pin rts low. d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock write us_cr txrdy txempty stpbrk = 1 sttbrk = 1 break transmission end of break usart txd cts remote device rxd txd rxd rts rts cts
289 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 117. receiver behavior when operating with hardware handshaking figure 118 shows how the transmitter operates if hardware handshaking is enabled. the cts pin disables the transmitter. if a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin cts falls. figure 118. transmitter behavior when operating with hardware handshaking iso7816 mode the usart features an iso7816-compatible operating mode. this mode permits interfacing with smart cards and security access modules (sam) communicating through an iso7816 link. both t = 0 and t = 1 protocols defined by the iso7816 specification are supported. setting the usart in iso7816 mode is performed by writing the usart_mode field in the mode register (us_mr) to the value 0x4 for protocol t = 0 and to the value 0x5 for protocol t = 1. iso7816 mode overview the iso7816 is a half duplex communication on only one bidirectional line. the baud rate is determined by a division of the clock provided to the remote device (see ?baud rate genera- tor? on page 275). the usart connects to a smart card as shown in figure 119. the txd line becomes bidirec- tional and the baud rate generator feeds the iso7816 clock on the sck pin. as the txd pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. the usart is considered as the master of the communication as it generates the clock. figure 119. connection of a smart card to the usart when operating in iso7816, either in t = 0 or t = 1 modes, the character format is fixed. the configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values pro- grammed in the chrl, mode9, par and chmode fields. msbf can be used to transmit lsb or msb first. rts rxbuff write us_cr rxen = 1 rxd rxdis = 1 cts txd smart card sck clk txd i/o usart
290 at91sam7s64 preliminary 6070a?atarm?28-oct-04 the usart cannot operate concurrently in both receiver and transmitter modes as the com- munication is unidirectional at a time. it has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. enabling both the receiver and the transmitter at the same time in iso7816 mode may lead to unpredictable results. the iso7816 specification defines an inverse transmission format. data bits of the character must be transmitted on the i/o line at their negative value. the usart does not support this format and the user has to perform an exclusive or on the data before writing it in the trans- mit holding register (us_thr) or after reading it in the receive holding register (us_rhr). protocol t = 0 in t = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. the transmitter shifts out the bits and does not drive the i/o line during the guard time. if no parity error is detected, the i/o line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in figure 120. if a parity error is detected by the receiver, it drives the i/o line at 0 during the guard time, as shown in figure 121. this error bit is also named nack, for non acknowledge. in this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. when the usart is the receiver and it detects an error, it does not load the erroneous charac- ter in the receive holding register (us_rhr). it appropriately sets the pare bit in the status register (us_sr) so that the software can handle the error. figure 120. t = 0 protocol without parity error figure 121. t = 0 protocol with parity error receive error counter the usart receiver also records the total number of errors. this can be read in the number of error (us_ner) register. the nb_errors field can record up to 255 errors. reading us_ner automatically clears the nb_errors field. receive nack inhibit the usart can also be configured to inhibit an error. this can be achieved by setting the inack bit in the mode register (us_mr). if inack is at 1, no error signal is driven on the i/o line even if a parity bit is detected, but the inack bit is set in the status register (us_sr). the inack bit can be cleared by writing the control register (us_cr) with the rstnack bit at 1. d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit baud rate clock start bit guard time 1 next start bit guard time 2 d0 d1 d2 d3 d4 d5 d6 d7 i/o parity bit baud rate clock start bit guard time 1 start bit guard time 2 d0 d1 error repetition
291 at91sam7s64 preliminary 6070a?atarm?28-oct-04 moreover, if inack is set, the erroneous received character is stored in the receive holding register, as if no error occurred. however, the rxrdy bit does not raise. transmit character repetition when the usart is transmitting a character and gets a nack, it can automatically repeat the character before moving on to the next one. repetition is enabled by writing the max_iteration field in the mode register (us_mr) at a value higher than 0. each charac- ter can be transmitted up to eight times; the first transmission plus seven repetitions. if max_iteration does not equal zero, the usart repeats the character as many times as the value loaded in max_iteration. when the usart repetition number reaches max_iteration, the iteration bit is set in the channel status register (us_csr). if the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. the iteration bit in us_csr can be cleared by writing the control register with the rsit bit at 1. disable successive receive nack the receiver can limit the number of successive nacks sent back to the remote transmitter. this is programmed by setting the bit dsnack in the mode register (us_mr). the maximum number of nack transmitted is programmed in the max_iteration field. as soon as max_iteration is reached, the character is considered as correct, an acknowledge is sent on the line and the iteration bit in the channel status register is set. protocol t = 1 when operating in iso7816 protocol t = 1, the transmission is similar to an asynchronous for- mat with only one stop bit. the parity is generated when transmitting and checked when receiving. parity error detection sets the pare bit in the channel status register (us_csr). irda mode the usart features an irda mode supplying half-duplex point-to-point wireless communica- tion. it embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in figure 122. the modulator and demodulator are compliant with the irda specification version 1.1 and support data transfer speeds ranging from 2.4 kb/s to 115.2 kb/s. the usart irda mode is enabled by setting the usart_mode field in the mode register (us_mr) to the value 0x8. the irda filter register (us_if) allows configuring the demodula- tor filter. the usart transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. note that the modulator and the demodulator are activated. figure 122. connection to irda transceivers the receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. irda transceivers rxd rx txd tx usart demodulator modulator receiver transmitter
292 at91sam7s64 preliminary 6070a?atarm?28-oct-04 irda modulation for baud rates up to and including 115.2 kbits/sec, the rzi modulation scheme is used. "0" is represented by a light pulse of 3/16th of a bit time. some examples of signal pulse duration are shown in table 66. figure 123 shows an example of character transmission. figure 123. irda modulation irda baud rate table 67 gives some examples of cd values, baud rate error and pulse duration. note that the requirement on the maximum acceptable error of 1.87% must be met. table 66. irda pulse duration baud rate pulse duration (3/16) 2.4 kb/s 78.13 s 9.6 kb/s 19.53 s 19.2 kb/s 9.77 s 38.4 kb/s 4.88 s 57.6 kb/s 3.26 s 115.2 kb/s 1.63 s bit period bit period 3 16 start bit data bits start bit 0 0 0 0 0 1 1 1 1 1 transmitter output txd table 67. irda baud rate error peripheral clock baud rate cd baud rate error pulse time 3 686 400 115 200 2 0.00% 1.63 20 000 000 115 200 11 1.38% 1.63 32 768 000 115 200 18 1.25% 1.63 40 000 000 115 200 22 1.38% 1.63 3 686 400 57 600 4 0.00% 3.26 20 000 000 57 600 22 1.38% 3.26 32 768 000 57 600 36 1.25% 3.26 40 000 000 57 600 43 0.93% 3.26 3 686 400 38 400 6 0.00% 4.88 20 000 000 38 400 33 1.38% 4.88 32 768 000 38 400 53 0.63% 4.88 40 000 000 38 400 65 0.16% 4.88
293 at91sam7s64 preliminary 6070a?atarm?28-oct-04 irda demodulator the demodulator is based on the irda receive filter comprised of an 8-bit down counter which is loaded with the value programmed in us_if. when a falling edge is detected on the rxd pin, the filter counter starts counting down at the master clock (mck) speed. if a rising edge is detected on the rxd pin, the counter stops and is reloaded with us_if. if no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. figure 124 illustrates the operations of the irda demodulator. figure 124. irda demodulator operations as the irda mode uses the same logic as the iso7816, note that the fi_di_ratio field in us_fidi must be set to a value higher than 0 in order to assure irda communications operate correctly. 3 686 400 19 200 12 0.00% 9.77 20 000 000 19 200 65 0.16% 9.77 32 768 000 19 200 107 0.31% 9.77 40 000 000 19 200 130 0.16% 9.77 3 686 400 9 600 24 0.00% 19.53 20 000 000 9 600 130 0.16% 19.53 32 768 000 9 600 213 0.16% 19.53 40 000 000 9 600 260 0.16% 19.53 3 686 400 2 400 96 0.00% 78.13 20 000 000 2 400 521 0.03% 78.13 32 768 000 2 400 853 0.04% 78.13 table 67. irda baud rate error (continued) peripheral clock baud rate cd baud rate error pulse time mck rxd receiver input pulse rejected 65432 6 1 driven low during 16 baud rate clock cycles 65432 0 pulse accepted counter value
294 at91sam7s64 preliminary 6070a?atarm?28-oct-04 rs485 mode the usart features the rs485 mode to enable line driver control. while operating in rs485 mode, the usart behaves as though in asynchronous or synchronous mode and configura- tion of all the parameters is possible. the difference is that the rts pin is driven high when the transmitter is operating. the behavior of the rts pin is controlled by the txempty bit. a typ- ical connection of the usart to a rs485 bus is shown in figure 125. figure 125. typical connection to a rs485 bus the usart is set in rs485 mode by programming the usart_mode field in the mode reg- ister (us_mr) to the value 0x1. the rts pin is at a level inverse to the txempty bit. significantly, the rts pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. figure 126 gives an example of the rts waveform during a character transmis- sion when the timeguard is enabled. figure 126. example of rts drive with timeguard usart rts txd rxd differential bus d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock tg = 4 write us_thr txrdy txempty rts
295 at91sam7s64 preliminary 6070a?atarm?28-oct-04 modem mode the usart features modem mode, which enables control of the signals: dtr (data terminal ready), dsr (data set ready), rts (request to send), cts (clear to send), dcd (data carrier detect) and ri (ring indicator). while operating in modem mode, the usart behaves as a dte (data terminal equipment) as it drives dtr and rts and can detect level change on dsr, dcd, cts and ri. setting the usart in modem mode is performed by writing the usart_mode field in the mode register (us_mr) to the value 0x3. while operating in modem mode the usart behaves as though in asynchronous mode and all the parameter configurations are available. table 68 gives the correspondence of the usart signals with modem connection standards. the control of the rts and dtr output pins is performed by witting the control register (us_cr) with the rtsdis, rtsen, dtrdis and dtren bits respectively at 1. the disable command forces the corresponding pin to its inactive level, i.e. high. the enable commands force the corresponding pin to its active level, i.e. low. the level changes are detected on the ri, dsr, dcd and cts pins. if an input change is detected, the riic, dsric, dcdic and ctsic bits in the channel status register (us_csr) are set respectively and can trigger an interrupt. the status is automatically cleared when us_csr is read. furthermore, the cts automatically disables the transmitter when it is detected at its inactive state. if a character is being transmitted when the cts rises, the char- acter transmission is completed before the transmitter is actually disabled. table 68. circuit references usart pin v24 ccitt direction txd 2 103 from terminal to modem rts 4 105 from terminal to modem dtr 20 108.2 from terminal to modem rxd 3 104 from modem to terminal cts 5 106 from terminal to modem dsr 6 107 from terminal to modem dcd 8 109 from terminal to modem ri 22 125 from terminal to modem
296 at91sam7s64 preliminary 6070a?atarm?28-oct-04 test modes the usart can be programmed to operate in three different test modes. the internal loop- back capability allows on-board diagnostics. in the loopback mode the usart interface pins are disconnected or not and reconfigured for loopback internally or externally. normal mode normal mode connects the rxd pin on the receiver input and the transmitter output on the txd pin. figure 127. normal mode configuration automatic echo mode automatic echo mode allows bit-by-bit retransmission. when a bit is received on the rxd pin, it is sent to the txd pin, as shown in figure 128. programming the transmitter has no effect on the txd pin. the rxd pin is still connected to the receiver input, thus the receiver remains active. figure 128. automatic echo mode configuration local loopback mode local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in figure 129. the txd and rxd pins are not used. the rxd pin has no effect on the receiver and the txd pin is continuously driven high, as in idle state. figure 129. local loopback mode configuration remote loopback mode remote loopback mode directly connects the rxd pin to the txd pin, as shown in figure 130. the transmitter and the receiver are disabled and have no effect. this mode allows bit-by-bit retransmission. receiver transmitter rxd txd receiver transmitter rxd txd receiver transmitter rxd txd 1
297 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 130. remote loopback mode configuration receiver transmitter rxd txd 1
298 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usart user interface table 69. usart register mapping offset register name access reset state 0x0000 control register us_cr write-only ? 0x0004 mode register us_mr read/write ? 0x0008 interrupt enable register us_ier write-only ? 0x000c interrupt disable register us_idr write-only ? 0x0010 interrupt mask register us_imr read-only 0 0x0014 channel status register us_csr read-only ? 0x0018 receiver holding register us_rhr read-only 0 0x001c transmitter holding register us_thr write-only ? 0x0020 baud rate generator register us_brgr read/write 0 0x0024 receiver time-out register us_rtor read/write 0 0x0028 transmitter timeguard register us_ttgr read/write 0 0x002c - 0x003c reserved ? ? ? 0x0040 fi di ratio register us_fidi read/write 0x174 0x0044 number of errors register us_ner read-only ? 0x0048 reserved ? ? ? 0x004c irda filter register us_if read/write 0 0x0050 - 0x00fc reserved ? ? ? 0x0100 - 0x0128 reserved for pdc registers ? ? ?
299 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usart control register name: us_cr access type: write-only rstrx: reset receiver 0: no effect. 1: resets the receiver. rsttx: reset transmitter 0: no effect. 1: resets the transmitter. rxen: receiver enable 0: no effect. 1: enables the receiver, if rxdis is 0. rxdis: receiver disable 0: no effect. 1: disables the receiver. txen: transmitter enable 0: no effect. 1: enables the transmitter if txdis is 0. txdis: transmitter disable 0: no effect. 1: disables the transmitter. rststa: reset status bits 0: no effect. 1: resets the status bits pare, frame, ovre and rxbrk in the us_csr. sttbrk: start break 0: no effect. 1: starts transmission of a break after the characters present in us_thr and the transmit shift register have been trans- mitted. no effect if a break is already being transmitted. stpbrk: stop break 0: no effect. 1: stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. no effect if no break is being transmitted. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????rtsdisrtsendtrdisdtren 15 14 13 12 11 10 9 8 retto rstnack rstit senda sttto stpbrk sttbrk rststa 76543210 txdis txen rxdis rxen rsttx rstrx ? ?
300 at91sam7s64 preliminary 6070a?atarm?28-oct-04 sttto: start time-out 0: no effect 1: starts waiting for a character before clocking the time-out counter. senda: send address 0: no effect. 1: in multi-drop mode only, the next character written to the us_thr is sent with the address bit set. rstit: reset iterations 0: no effect. 1: resets iteration in us_csr. no effect if the iso7816 is not enabled. rstnack: reset non acknowledge 0: no effect 1: resets nack in us_csr. retto: rearm time-out 0: no effect 1: restart time-out dtren: data terminal ready enable 0: no effect. 1: drives the pin dtr at 0. dtrdis: data terminal ready disable 0: no effect. 1: drives the pin dtr to 1. rtsen: request to send enable 0: no effect. 1: drives the pin rts to 0. rtsdis: request to send disable 0: no effect. 1: drives the pin rts to 1.
301 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usart mode register name: us_mr access type: read/write usart_mode usclks: clock selection chrl: character length. 31 30 29 28 27 26 25 24 ? ? ? filter ? max_iteration 23 22 21 20 19 18 17 16 ? ? dsnack inack over clko mode9 msbf 15 14 13 12 11 10 9 8 chmode nbstop par sync 76543210 chrl usclks usart_mode usart_mode mode of the usart 0000normal 0001rs485 0010hardware handshaking 0011m odem 0100is 07816 protocol: t = 0 0101reserved 0110is 07816 protocol: t = 1 0111reserved 1000irda 11xxreserved usclks selected clock 00mck 01mck / div 10reserved 11sck chrl character length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits
302 at91sam7s64 preliminary 6070a?atarm?28-oct-04 sync: synchronous mode select 0: usart operates in asynchronous mode. 1: usart operates in synchronous mode. par: parity type nbstop: number of stop bits chmode: channel mode msbf: bit order 0: least significant bit is sent/received first. 1: most significant bit is sent/received first. mode9: 9-bit character length 0: chrl defines c haracter length. 1: 9-bit character length. cklo: clock output select 0: the usart does not drive the sck pin. 1: the usart drives the sck pin if usclks does not select the external clock sck. over: oversampling mode 0: 16x oversampling. 1: 8x oversampling. par parity type 0 0 0 even parity 001odd parity 0 1 0 parity forced to 0 (space) 0 1 1 parity forced to 1 (mark) 10xno parity 1 1 x multi-drop mode nbstop asynchronous (sync = 0) synchronous (sync = 1) 0 0 1 stop bit 1 stop bit 0 1 1.5 stop bits reserved 1 0 2 stop bits 2 stop bits 1 1 reserved reserved chmode mode description 0 0 normal mode 0 1 automatic echo. receiver input is connected to the txd pin. 1 0 local loopback. transmitter output is connected to the receiver input.. 1 1 remote loopback. rxd pin is internally connected to the txd pin.
303 at91sam7s64 preliminary 6070a?atarm?28-oct-04 inack: inhibit non acknowledge 0: the nack is generated. 1: the nack is not generated. dsnack: disable successive nack 0: nack is sent on the iso line as soon as a parity error occurs in the received character (unless inack is set). 1: successive parity errors are counted up to the value specified in the max_iteration field. these parity errors gener- ate a nack on the iso line. as soon as this value is reached, no additional nack is sent on the iso line. the flag iteration is asserted. max_iteration defines the maximum number of iterations in mode iso7816, protocol t= 0. filter: infrared receive line filter 0: the usart does not filter the receive line. 1: the usart filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).
304 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usart interrupt enable register name: us_ier access type: write-only rxrdy: rxrdy interrupt enable txrdy: txrdy interrupt enable rxbrk: receiver break interrupt enable endrx: end of receive transfer interrupt enable endtx: end of transmit interrupt enable ovre: overrun error interrupt enable frame: framing error interrupt enable pare: parity error interrupt enable timeout: time-out interrupt enable txempty: txempty interrupt enable iteration: iteration interrupt enable txbufe: buffer empty interrupt enable rxbuff: buffer full interrupt enable nack: non acknowledge interrupt enable riic: ring indicator input change enable dsric: data set ready input change enable dcdic: data carrier detect input change interrupt enable ctsic: clear to send input change interrupt enable 0: no effect. 1: enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????ctsicdcdicdsricriic 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
305 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usart interrupt disable register name: us_idr access type: write-only rxrdy: rxrdy interrupt disable txrdy: txrdy interrupt disable rxbrk: receiver break interrupt disable endrx: end of receive transfer interrupt disable endtx: end of transmit interrupt disable ovre: overrun error interrupt disable frame: framing error interrupt disable pare: parity error interrupt disable timeout: time-out interrupt disable txempty: txempty interrupt disable iteration: iteration interrupt disable txbufe: buffer empty interrupt disable rxbuff: buffer full interrupt disable nack: non acknowledge interrupt disable riic: ring indicator input change disable dsric: data set ready input change disable dcdic: data carrier detect input change interrupt disable ctsic: clear to send input change interrupt disable 0: no effect. 1: disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????ctsicdcdicdsricriic 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
306 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usart interrupt mask register name: us_imr access type: read-only rxrdy: rxrdy interrupt mask txrdy: txrdy interrupt mask rxbrk: receiver break interrupt mask endrx: end of receive transfer interrupt mask endtx: end of transmit interrupt mask ovre: overrun error interrupt mask frame: framing error interrupt mask pare: parity error interrupt mask timeout: time-out interrupt mask txempty: txempty interrupt mask iteration: iteration interrupt mask txbufe: buffer empty interrupt mask rxbuff: buffer full interrupt mask nack: non acknowledge interrupt mask riic: ring indicator input change mask dsric: data set ready input change mask dcdic: data carrier detect input change interrupt mask ctsic: clear to send input change interrupt mask 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????ctsicdcdicdsricriic 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
307 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usart channel status register name: us_csr access type: read-only rxrdy: receiver ready 0: no complete character has been received since the last read of us_rhr or the receiver is disabled. if characters were being received when the receiver was disabled, rxrdy changes to 1 when the receiver is enabled. 1: at least one complete character has been received and us_rhr has not yet been read. txrdy: transmitter ready 0: a character is in the us_thr waiting to be transferred to the transmit shift register, or an sttbrk command has been requested, or the transmitter is disabled. as soon as the transmitter is enabled, txrdy becomes 1. 1: there is no character in the us_thr. rxbrk: break received/end of break 0: no break received or end of break detected since the last rststa. 1: break received or end of break detected since the last rststa. endrx: end of receiver transfer 0: the end of transfer signal from the receive pdc channel is inactive. 1: the end of transfer signal from the receive pdc channel is active. endtx: end of transmitter transfer 0: the end of transfer signal from the transmit pdc channel is inactive. 1: the end of transfer signal from the transmit pdc channel is active. ovre: overrun error 0: no overrun error has occurred since since the last rststa. 1: at least one overrun error has occurred since the last rststa. frame: framing error 0: no stop bit has been detected low since the last rststa. 1: at least one stop bit has been detected low since the last rststa. pare: parity error 0: no parity error has been detected since the last rststa. 1: at least one parity error has been detected since the last rststa. timeout: receiver time-out 0: there has not been a time-out since the last star t time-out command or the time-out register is 0. 1: there has been a time-out since the last start time-out command. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 cts dcd dsr ri ctsic dcdic dsric riic 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy
308 at91sam7s64 preliminary 6070a?atarm?28-oct-04 txempty: transmitter empty 0: there are characters in either us_thr or the transmit shift register, or the transmitter is disabled. 1: there is at least one character in either us_thr or the transmit shift register. iteration: max number of repetitions reached 0: maximum number of repetitions has not been reached since the last rsit. 1: maximum number of repetitions has been reached since the last rsit. txbufe: transmission buffer empty 0: the signal buffer empty from the transmit pdc channel is inactive. 1: the signal buffer empty from the transmit pdc channel is active. rxbuff: reception buffer full 0: the signal buffer full from the receive pdc channel is inactive. 1: the signal buffer full from the receive pdc channel is active. nack: non acknowledge 0: no non acknowledge has not been detected since the last rstnack. 1: at least one non acknowledge has been detected since the last rstnack. riic: ring indicator input change flag 0: no input change has been detected on the ri pin since the last read of us_csr. 1: at least one input change has been detected on the ri pin since the last read of us_csr. dsric: data set ready input change flag 0: no input change has been detected on the dsr pin since the last read of us_csr. 1: at least one input change has been detected on the dsr pin since the last read of us_csr. dcdic: data carrier detect input change flag 0: no input change has been detected on the dcd pin since the last read of us_csr. 1: at least one input change has been detected on the dcd pin since the last read of us_csr. ctsic: clear to send input change flag 0: no input change has been detected on the cts pin since the last read of us_csr. 1: at least one input change has been detected on the cts pin since the last read of us_csr. ri: image of ri input 0: ri is at 0. 1: ri is at 1. dsr: image of dsr input 0: dsr is at 0 1: dsr is at 1. dcd: image of dcd input 0: dcd is at 0. 1: dcd is at 1. cts: image of cts input 0: cts is at 0. 1: cts is at 1.
309 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usart receive holding register name: us_rhr access type: read-only rxchr: received character last character received if rxrdy is set. usart transmit holding register name: us_thr access type: write-only txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????rxchr 76543210 rxchr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????txchr 76543210 txchr
310 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usart baud rate generator register name: us_brgr access type: read/write cd: clock divider 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cd 76543210 cd cd usart_mode iso7816 usart_mode = iso7816 sync = 0 sync = 1 over = 0 over = 1 0 baud rate clock disabled 1 to 65535 baud rate = selected clock/16/cd baud rate = selected clock/8/cd baud rate = selected clock /cd baud rate = selected clock/cd/fi_di_ratio
311 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usart receiver time-out register name: us_rtor access type: read/write to: time-out value 0: the receiver time-out is disabled. 1 - 65535: the receiver time-out is enabled and the time-out delay is to x bit period. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 to 76543210 to
312 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usart transmitter timeguard register name: us_ttgr access type: read/write tg: timeguard value 0: the transmitter timeguard is disabled. 1 - 255: the transmitter timeguard is enabled and the timeguard delay is tg x bit period. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 tg
313 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usart fi di ratio register name: us_fidi access type: read/write reset value: 0x174 fi_di_ratio: fi over di ratio value 0: if iso7816 mode is selected, the baud rate generator generates no signal. 1 - 2047: if iso7816 mode is selected, the baud rate is the clock provided on sck divided by fi_di_ratio. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? fi_di_ratio 76543210 fi_di_ratio
314 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usart number of errors register name: us_ner access type: read-only nb_errors: number of errors total number of errors that occurred during an iso7816 tr ansfer. this register automatically clears when read. usart irda filter register name: us_if access type: read/write irda_filter: irda filter sets the filter of the irda demodulator. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 nb_errors 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 irda_filter
315 at91sam7s64 preliminary 6070a?atarm?28-oct-04 synchronous serial controller (ssc) overview the atmel synchronous serial controller (ssc) provides a synchronous communication link with external devices. it supports many serial synchronous communication protocols generally used in audio and telecom applications such as i2s, short frame sync, long frame sync, etc. the ssc contains an independent receiver and transmitter and a common clock divider. the receiver and the transmitter each interface with three signals: the td/rd signal for data, the tk/rk signal for the clock and the tf/rf signal for the frame sync. transfers contain up to 16 data of up to 32 bits. they can be programmed to start automatically or on different events detected on the frame sync signal. the ssc?s high-level of programmability and its two dedicated pdc channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention. featuring connection to two pdc channels, the ssc permits interfacing with low processor overhead to the following: codec?s in master or slave mode dac through dedicated serial interface, particularly i2s magnetic card reader block diagram figure 131. block diagram ssc interface pio pdc apb bridge mck asb apb tf tk td rf rk rd interrupt control ssc interrupt pmc
316 at91sam7s64 preliminary 6070a?atarm?28-oct-04 application block diagram figure 132. application block diagram interrupt management power management test management ssc serial audio os or rtos driver codec frame management line interface time slot management
317 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pin name list product dependencies i/o lines the pins used for interfacing the compliant external devices may be multiplexed with pio lines. before using the ssc receiver, the pio controller must be configured to dedicate the ssc receiver i/o lines to the ssc peripheral mode. before using the ssc transmitter, the pio controller must be configured to dedicate the ssc transmitter i/o lines to the ssc peripheral mode. power management the ssc is not continuously clocked. the ssc interface may be clocked through the power management controller (pmc), therefore the programmer must first configure the pmc to enable the ssc clock. interrupt the ssc interface has an interrupt line connected to the advanced interrupt controller (aic). handling interrupts requires programming the aic before configuring the ssc. all ssc interrupts can be enabled/disabled configuring the ssc interrupt mask register. each pending and unmasked ssc interrupt will assert the ssc interrupt line. the ssc interrupt ser- vice routine can get the interrupt origin by reading the ssc interrupt status register. functional description this chapter contains the functional description of the following: ssc functional block, clock management, data format, start, transmitter, receiver and frame sync. the receiver and transmitter operate separately. however, they can work synchronously by programming the receiver to use the transmit clo ck and/or to start a data transfer when trans- mission starts. alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. the transmitter and the receiver can be programmed to operate with the clock signals provided on either the tk or rk pins. this allows the ssc to support many slave-mode data transfers. the maximum clock speed allowed on the tk and rk pins is the master clock divided by 2. each level of the clock must be stable for at least two master clock periods. table 70. i/o lines description pin name pin description type rf receiver frame synchro input/output rk receiver clock input/output rd receiver data input tf transmitter frame synchro input/output tk transmitter clock input/output td transmitter data output
318 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 133. ssc functional block diagram clock management the transmitter clock can be generated by: an external clock received on the tk i/o pad the receiver clock the internal clock divider the receiver clock can be generated by: an external clock received on the rk i/o pad the transmitter clock the internal clock divider furthermore, the transmitter block can generate an external clock on the tk i/o pad, and the receiver block can generate an external clock on the rk i/o pad. this allows the ssc to support many master and slave-mode data transfers. interrupt control aic user interface apb mck receive clock controller start selector tx clock rk input rf tf clock output controller frame sync controller transmit clock controller transmit shift register start selector transmit sync holding register transmit holding register load shift rx clock tx clock tk input tf tx pdc rf rd rf rk clock output controller frame sync controller receive shift register receive sync holding register receive holding register load shift td tf tk rx clock rx pdc receiver pdc transmitter clock divider
319 at91sam7s64 preliminary 6070a?atarm?28-oct-04 clock divider figure 134. divided clock block diagram the master clock divider is determined by the 12-bit field div counter and comparator (so its maximal value is 4095) in the clock mode register ssc_cmr, allowing a master clock divi- sion by up to 8190. the divided clock is provided to both the receiver and transmitter. when this field is programmed to 0, the clock divider is not used and remains inactive. when div is set to a value equal or greater to 1, the divided clock has a frequency of master clock divided by 2 times div. each level of the divided clock has a duration of the master clock multiplied by div. this ensures a 50% duty cycle for the divided clock regardless if the div value is even or odd. figure 135. divided clock generation transmitter clock management the transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the tk i/o pad. the transmitter clock is selected by the cks field in ssc_tcmr (transmit clock mode register). transmit clock can be inverted independently by the cki bits in ssc_tcmr. the transmitter can also drive the tk i/o pad continuously or be limited to the actual data transfer. the clock output is configured by the ssc_tcmr register. the transmit clock inver- sion (cki) bits have no effect on the clock outputs. programming the tcmr register to select tk pin (cks field) and at the same time continuous transmit clock (cko field) might lead to unpredictable results. table 71. bit rate maximum minimum mck / 2 mck / 8190 mck divided clock clock divider / 2 12-bit counter ssc_cmr master clock divided clock div = 1 master clock divided clock div = 3 divided clock frequency = mck/2 divided clock frequency = mck/6
320 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 136. transmitter clock management receiver clock management the receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the rk i/o pad. the receive clock is selected by the cks field in ssc_rcmr (receive clock mode register). receive clocks can be inverted independently by the cki bits in ssc_rcmr. the receiver can also drive the rk i/o pad continuously or be limited to the actual data trans- fer. the clock output is configured by the ssc_rcmr register. the receive clock inversion (cki) bits have no effect on the clock outputs. programming the rcmr register to select rk pin (cks field) and at the same time continuous receive clock (cko field) might lead to unpredictable results. figure 137. receiver clock management receiver clock divider clock transmitter clock ssc_tcmr.cki ssc_tcmr.cks tk ssc_tcmr.cko 1 0 tk transmitter clock divider clock receiver clock ssc_rcmr.cki ssc_rcmr.cks rk ssc_rcmr.cko 1 0 rk
321 at91sam7s64 preliminary 6070a?atarm?28-oct-04 transmitter operations a transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. the start event is configured by setting the transmit clock mode register (ssc_tcmr). see ?start? on page 322. the frame synchronization is configured setting the transmit frame mode register (ssc_tfmr). see ?frame sync? on page 324. to transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the ssc_tcmr. data is written by the application to the ssc_thr register then transferred to the shift register according to the data format selected. when both the ssc_thr and the transmit shift register are empty, the status flag txempty is set in ssc_sr. when the transmit holding register is transferred in the transmit shift reg- ister, the status flag txrdy is set in ssc_sr and additional data can be loaded in the holding register. figure 138. transmitter block diagram transmit shift register start selector ssc_tshr ssc_thr transmitter clock td ssc_tfmr.fslen ssc_tfmr.datlen ssc_cr.txen ssc_cr.txdis ssc_tcmr.sttdly ssc_tfmr.fsden ssc_tfmr.datnb ssc_sr.txen ssc_tfmr.datdef ssc_tfmr.msbf ssc_tcmr.sttdly ssc_tfmr.fsden 0 1 1 0 rf tf
322 at91sam7s64 preliminary 6070a?atarm?28-oct-04 receiver operations a received frame is triggered by a start event and can be followed by synchronization data before data transmission. the start event is configured setting the receive clock mode register (ssc_rcmr). see ?start? on page 322. the frame synchronization is configured setting the receive frame mode register (ssc_rfmr). see ?frame sync? on page 324. the receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the ssc_rcmr. the data is transferred from the shift register in function of data format selected. when the receiver shift register is full, the ssc transfers this data in the holding register, the status flag rxrdy is set in ssc_sr and the data can be read in the receiver holding register, if another transfer occurs before read the rhr register, the status flag overun is set in ssc_sr and the receiver shift register is transferred in the rhr register. figure 139. receiver block diagram start the transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the transmit start selection (start) field of ssc_tcmr and in the receive start selection (start) field of ssc_rcmr. under the following conditions the start event is independently programmable: continuous. in this case, the transmission starts as soon as a word is written in ssc_thr and the reception starts as soon as the receiver is enabled. synchronously with the transmitter/receiver on detection of a falling/rising edge on tk/rk on detection of a low level/high level on tk/rk on detection of a level change or an edge on tk/rk a start can be programmed in the same manner on either side of the transmit/receive clock register (rcmr/tcmr). thus, the start could be on tf (transmit) or rf (receive). detection on tf/rf input/output is done through the field fsos of the transmit/receive frame mode register (tfmr/rfmr). receive shift register start selector ssc_rhr ssc_rshr receiver clock rd ssc_rfmr.fslen ssc_rfmr.datlen rf ssc_cr.rxen ssc_cr.rxdis ssc_sr.rxen ssc_rfmr.msbf ssc_rcmr.sttdly ssc_rfmr.datnb tf
323 at91sam7s64 preliminary 6070a?atarm?28-oct-04 generating a frame sync signal is not possible without generating it on its related output. figure 140. transmit start mode figure 141. receive pulse/edge start modes x tk tf (input) td (output) td (output) td (output) td (output) td (output) td (output) xbob1 x bo b1 bo b1 bo b1 bo b1 bo b1 bo b1 b1 bo x x x sttdly sttdly sttdly sttdly sttdly sttdly start = falling edge on tf start = rising edge on tf start = low level on tf start = high level on tf start = any edge on tf start = level change on tf x rk rf (input) rd (input) rd (input) rd (input) rd (input) rd (input) rd (input) xbob1 x bo b1 bo b1 bo b1 bo b1 bo b1 bo b1 b1 bo x x x sttdly sttdly sttdly sttdly sttdly sttdly start = falling edge on rf start = rising edge on rf start = low level on rf start = high level on rf start = any edge on rf start = level change on rf
324 at91sam7s64 preliminary 6070a?atarm?28-oct-04 frame sync the transmitter and receiver frame sync pins, tf and rf, can be programmed to generate different kinds of frame synchronization signals. the frame sync output selection (fsos) field in the receive frame mode register (ssc_rfmr) and in the transmit frame mode register (ssc_tfmr) are used to select the required waveform. programmable low or high levels during data transfer are supported. programmable high levels before the start of da ta transfers or toggling are also supported. if a pulse waveform is selected, the frame sync length (fslen) field in ssc_rfmr and ssc_tfmr programs the length of the pulse, from 1-bit time up to 16-bit time. the periodicity of the receive and transmit frame sync pulse output can be programmed through the period divider selection (period) field in ssc_rcmr and ssc_tcmr. frame sync data frame sync data transmits or receives a specific tag during the frame synchro signal. during the frame sync signal, the receiver can sample the rd line and store the data in the receive sync holding register and the transmitter can transfer transmit sync holding regis- ter in the shifter register. the data length to be sampled/shifted out during the frame sync signal is programmed by the fslen field in ssc_rfmr/ssc_tfmr. concerning the receive frame sync data operation, if the frame sync length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the receive sync holding register through the receive shift register. the transmit frame sync operation is performed by the transmitter only if the bit frame sync data enable (fsden) in ssc_tfmr is set. if the frame sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the transmit sync holding register is transferred in the transmit register then shifted out. frame sync edge detection the frame sync edge detection is programmed by the fsedge field in ssc_rfmr/ssc_tfmr. this sets the corresponding flags rxsyn/txsyn in the ssc sta- tus register (ssc_sr) on frame synchro edge detection (signals rf/tf). data format the data framing format of both the transmitter and the receiver are largely programmable through the transmitter frame mode register (ssc_tfmr) and the receiver frame mode register (ssc_rfmr). in either ca se, the user can independently select: the event that starts the data transfer (start). the delay in number of bit periods between the start event and the first data bit ( sttdly ). the length of the data (datlen) the number of data to be transferred for each start event (datnb). the length of synchronization transferred for each start event (fslen). the bit sense: most or lowest significant bit first (msbf). additionally, the transmitter can be used to transfer synchronization and select the level driven on the td pin while not in data transfer operation. this is done respectively by the frame sync data enable (fsden) and by the data default value (datdef) bits in ssc_tfmr.
325 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 142. transmit and receive frame format in edge/pulse start modes note: 1. example of input on falling edge of tf/rf. table 72. data frame registers transmitter receiver field length comment ssc_tfmr ssc_rfmr datlen up to 32 size of word ssc_tfmr ssc_rfmr datnb up to 16 number word transmitter in frame ssc_tfmr ssc_rfmr msbf 1 most significant bit in first ssc_tfmr ssc_rfmr fslen up to 16 size of synchro data register ssc_tfmr datdef 0 or 1 data default value ended ssc_tfmr fsden enable send ssc_tshr ssc_tcmr ssc_rcmr period up to 512 frame size ssc_tcmr ssc_rcmr sttdly up to 255 size of transmit start delay sync data default sttdly sync data ignored rd default data datlen data data data datlen data data default default ignored sync data sync data fslen tf/rf (1) start start from ssc_tshr from ssc_thr from ssc_thr from ssc_thr from ssc_thr to ssc_rhr to ssc_rhr to ssc_rshr td (if fsden = 0) td (if fsden = 1) datnb period fromdatdef fromdatdef from datdef from datdef
326 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 143. transmit frame format in continuous mode note: 1. sttdly is set to 0. in this example, ssc_thr is loaded twice. fsden value has no effect on the transmission. syncdata cannot be output in continuous mode. figure 144. receive frame format in continuous mode note: 1. sttdly is set to 0. loop mode the receiver can be programmed to receive transmissions from the transmitter. this is done by setting the loop mode (loop) bit in ssc_rfmr. in this case, rd is connected to td, rf is connected to tf and rk is connected to tk. interrupt most bits in ssc_sr have a corresponding bit in interrupt management registers. the ssc controller can be programmed to generate an interrupt when it detects an event. the interrupt is controlled by writing ssc_ier (interrupt enable register) and ssc_idr (interrupt disable register), which respectively enable and disable the corresponding interrupt by setting and clearing the corresponding bit in ssc_imr (interrupt mask register), which controls the generation of interrupts by asserting the ssc interrupt line connected to the aic. datlen data datlen data default start from ssc_thr from ssc_thr td start: 1. txempty set to 1 2. write into the ssc_thr data datlen data datlen start = enable receiver to ssc_rhr to ssc_rhr rd
327 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 145. interrupt block diagram ssc_imr pdc interrupt control ssc interrupt set rxrdy ovrun rxsync receiver transmitter txrdy txempty txsync txbufe endtx rxbuff endrx clear ssc_ier ssc_idr
328 at91sam7s64 preliminary 6070a?atarm?28-oct-04 ssc application examples the ssc can support several serial communication modes used in audio or high speed serial links. some standard applications are shown in the following figures. all serial link applications supported by the ssc are not listed here. figure 146. audio application block diagram figure 147. codec application block diagram ssc rk rf rd td tf tk clock sck word select ws data sd i2s receiver clock sck word select ws data sd right channel left channel msb msb lsb ssc rk rf rd td tf tk serial data clock (sclk) frame sync (fsync) serial data out serial data in codec serial data clock (sclk) frame sync (fsync) serial data out serial data in first time slot dstart dend
329 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 148. time slot application block diagram ssc rk rf rd td tf tk sclk fsync data out data in codec first time slot serial data clock (sclk) frame sync (fsync) serial data out serial data in codec second time slot first time slot second time slot dstart dend
330 at91sam7s64 preliminary 6070a?atarm?28-oct-04 synchronous serial controller (ssc) user interface table 73. synchronous serial controller (ssc) register mapping offset register register name access reset 0x0 control register ssc_cr write ? 0x4 clock mode register ssc_cmr read/write 0x0 0x8 reserved ? ? ? 0xc reserved ? ? ? 0x10 receive clock mode register ssc_rcmr read/write 0x0 0x14 receive frame mode register ssc_rfmr read/write 0x0 0x18 transmit clock mode register ssc_tcmr read/write 0x0 0x1c transmit frame mode register ssc_tfmr read/write 0x0 0x20 receive holding register ssc_rhr read 0x0 0x24 transmit holding register ssc_thr write ? 0x28 reserved ? ? ? 0x2c reserved ? ? ? 0x30 receive sync. holding register ssc_rshr read 0x0 0x34 transmit sync. holding register ssc_tshr read/write 0x0 0x38 reserved ? ? ? 0x3c reserved ? ? ? 0x40 status register ssc_sr read 0x000000cc 0x44 interrupt enable register ssc_ier write ? 0x48 interrupt disable register ssc_idr write ? 0x4c interrupt mask register ssc_imr read 0x0 0x50-0xfc reserved ? ? ? 0x100 - 0x124 reserved for peripheral data controller (pdc) ? ? ?
331 at91sam7s64 preliminary 6070a?atarm?28-oct-04 ssc control register name: ssc_cr access type: write-only rxen: receive enable 0: no effect. 1: enables data receive if rxdis is not set (1) . rxdis: receive disable 0: no effect. 1: disables data receive (1) . txen: transmit enable 0: no effect. 1: enables data transmit if txdis is not set (1) . txdis: transmit disable 0: no effect. 1: disables data transmit (1) . swrst: software reset 0: no effect. 1: performs a software reset. has priority on any other bit in ssc_cr. note: 1. only the data management is affected ssc clock mode register name: ssc_cmr access type: read/write div: clock divider 0: the clock divider is not active. any other value: the divided clock equals the master clock divided by 2 times div. the maximum bit rate is mck/2. the minimum bit rate is mck/2 x 4095 = mck/8190. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 swrst?????txdistxen 76543210 ??????rxdisrxen 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? div 76543210 div
332 at91sam7s64 preliminary 6070a?atarm?28-oct-04 ssc receive clock mode register name: ssc_rcmr access type: read/write cks: receive clock selection cko: receive clock output mode selection cki: receive clock inversion 0: the data and the frame sync signal are sampled on receive clock falling edge. 1: the data and the frame sync signal are shifted out on receive clock rising edge. cki does not affect the rk output clock signal. 31 30 29 28 27 26 25 24 period 23 22 21 20 19 18 17 16 sttdly 15 14 13 12 11 10 9 8 ???? start 76543210 ? ? cki cko cks cks selected receive clock 0x0 divided clock 0x1 tk clock signal 0x2 rk pin 0x3 reserved cko receive clock output mode rk pin 0x0 none input-only 0x1 continuous receive clock output 0x2-0x7 reserved
333 at91sam7s64 preliminary 6070a?atarm?28-oct-04 start: receive start selection sttdly: receive start delay if sttdly is not 0, a delay of sttdly clock cycles is inserted between the start event and the actual start of reception. when the receiver is programmed to start synchronously with the transmitter, the delay is also applied. please note: it is very important that sttdly be set carefully. if sttdly must be set, it should be done in relation to tag (receive sync data) reception. period: receive period divider selection this field selects the divider to apply to the selected receive clock in order to generate a new frame sync signal. if 0, no period signal is generated. if not 0, a period signal is generated each 2 x (period+1) receive clock. start receive start 0x0 continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 0x1 transmit start 0x2 detection of a low level on rf input 0x3 detection of a high level on rf input 0x4 detection of a falling edge on rf input 0x5 detection of a rising edge on rf input 0x6 detection of any level change on rf input 0x7 detection of any edge on rf input 0x8-0xf reserved
334 at91sam7s64 preliminary 6070a?atarm?28-oct-04 ssc receive frame mode register name: ssc_rfmr access type: read/write datlen: data length 0x0 is not supported. the value of datlen can be set between 0x1 and 0x1f. the bit stream contains datlen + 1 data bits. moreover, it defines the transfer size performed by the pdc assigned to the receiver. if datlen is less than or equal to 7, data transfers are in bytes. if datlen is between 8 and 15 (included), half-words are transferred. for any other value, 32-bit words are transferred. loop: loop mode 0: normal operating mode. 1: rd is driven by td, rf is driven by tf and tk drives rk. msbf: most significant bit first 0: the lowest significant bit of the data register is sampled first in the bit stream. 1: the most significant bit of the data register is sampled first in the bit stream. datnb: data number per frame this field defines the number of data words to be received after each transfer start. if 0, only 1 data word is transferred. up to 16 data words can be transferred. fslen: receive frame sync length this field defines the length of the receive frame sync signal and the number of bits sampled and stored in the receive sync data register. only when fsos is set on negative or positive pulse. fsos: receive frame sync output selection 31 30 29 28 27 26 25 24 ???????fsedge 23 22 21 20 19 18 17 16 ? fsos fslen 15 14 13 12 11 10 9 8 ???? datnb 76543210 msbf ? loop datlen fsos selected receive frame sync signal rf pin 0x0 none input-only 0x1 negative pulse output 0x2 positive pulse output 0x3 driven low during data transfer output 0x4 driven high during data transfer output 0x5 toggling at each start of data transfer output 0x6-0x7 reserved undefined
335 at91sam7s64 preliminary 6070a?atarm?28-oct-04 fsedge: frame sync edge detection determines which edge on frame sync sets rxsyn in the ssc status register. fsedge frame sync edge detection 0x0 positive edge detection 0x1 negative edge detection
336 at91sam7s64 preliminary 6070a?atarm?28-oct-04 ssc transmit clock mode register name: ssc_tcmr access type: read/write cks: transmit clock selection cko: transmit clock output mode selection cki: transmit clock inversion 0: the data and the frame sync signal are shifted out on transmit clock falling edge. 1: the data and the frame sync signal are shifted out on transmit clock rising edge. cki affects only the transmit clock and not the output clock signal. 31 30 29 28 27 26 25 24 period 23 22 21 20 19 18 17 16 sttdly 15 14 13 12 11 10 9 8 ???? start 76543210 ? ? cki cko cks cks selected transmit clock 0x0 divided clock 0x1 rk clock signal 0x2 tk pin 0x3 reserved cko transmit clock output mode tk pin 0x0 none input-only 0x1 continuous transmit clock output 0x2-0x7 reserved
337 at91sam7s64 preliminary 6070a?atarm?28-oct-04 start: transmit start selection sttdly: transmit start delay if sttdly is not 0, a delay of sttdly clock cycles is insert ed between the start event and the actual start of transmission of data. when the transmitter is programmed to start synchronously with the receiver, the delay is also applied. please note: sttdly must be set carefully. if sttdly is too short in respect to tag (transmit sync data) emission, data is emitted instead of the end of tag. period: transmit period divider selection this field selects the divider to apply to the selected transmit clock to generate a new frame sync signal. if 0, no period signal is generated. if not 0, a period signal is generated at each 2 x (period+1) transmit clock. start transmit start 0x0 continuous, as soon as a word is written in the ssc_thr register (if transmit is enabled) and immediately after the end of transfer of the previous data. 0x1 receive start 0x2 detection of a low level on tf signal 0x3 detection of a high level on tf signal 0x4 detection of a falling edge on tf signal 0x5 detection of a rising edge on tf signal 0x6 detection of any level change on tf signal 0x7 detection of any edge on tf signal 0x8-0xf reserved
338 at91sam7s64 preliminary 6070a?atarm?28-oct-04 ssc transmit frame mode register name: ssc_tfmr access type: read/write datlen: data length 0x0 is not supported. the value of datlen can be set between 0x1 and 0x1f. the bit stream contains datlen + 1 data bits. moreover, it defines the transfer size performed by the pdc assigned to the receiver. if datlen is less than or equal to 7, data transfers are in bytes. if datlen is between 8 and 15 (included), half-words are transferred. for any other value, 32-bit words are transferred. datdef: data default value this bit defines the level driven on the td pin while out of transmission. note that if the pin is defined as multi-drive by th e pio controller, the pin is enabled only if the scc td output is 1. msbf: most significant bit first 0: the lowest significant bit of the data register is shifted out first in the bit stream. 1: the most significant bit of the data register is shifted out first in the bit stream. datnb: data number per frame this field defines the number of data words to be transferred after each transfer start. if 0, only 1 data word is transferred and up to 16 data words can be transferred. fslen: transmit frame sync length this field defines the length of the transmit frame sync signal and the number of bits shifted out from the transmit sync data register if fsden is 1. if 0, the transmit frame sync signal is generated during one transmit clock period and up to 16 clock period pulse length is possible. fsos: transmit frame sync output selection fsden: frame sync data enable 0: the td line is driven with the default value during the transmit frame sync signal. 1: ssc_tshr value is shifted out during the transmission of the transmit frame sync signal. 31 30 29 28 27 26 25 24 ???????fsedge 23 22 21 20 19 18 17 16 fsden fsos fslen 15 14 13 12 11 10 9 8 ???? datnb 76543210 msbf ? datdef datlen fsos selected transmit frame sync signal tf pin 0x0 none input-only 0x1 negative pulse output 0x2 positive pulse output 0x3 driven low during data transfer output 0x4 driven high during data transfer output 0x5 toggling at each start of data transfer output 0x6-0x7 reserved undefined
339 at91sam7s64 preliminary 6070a?atarm?28-oct-04 fsedge: frame sync edge detection determines which edge on frame sync sets txsyn (status register). fsedge frame sync edge detection 0x0 positive edge detection 0x1 negative edge detection
340 at91sam7s64 preliminary 6070a?atarm?28-oct-04 ssc receive holding register name: ssc_rhr access type : read-only rdat: receive data right aligned regardless of the number of data bits defined by datlen in ssc_rfmr. ssc transmit holding register name: ssc_thr access type: write only tdat: transmit data right aligned regardless of the number of data bits defined by datlen in ssc_tfmr. 31 30 29 28 27 26 25 24 rdat 23 22 21 20 19 18 17 16 rdat 15 14 13 12 11 10 9 8 rdat 76543210 rdat 31 30 29 28 27 26 25 24 tdat 23 22 21 20 19 18 17 16 tdat 15 14 13 12 11 10 9 8 tdat 76543210 tdat
341 at91sam7s64 preliminary 6070a?atarm?28-oct-04 ssc receive synchronization holding register name: ssc_rshr access type : read/write rsdat: receive synchronization data right aligned regardless of the number of data bits defined by fslen in ssc_rfmr. ssc transmit synchronization holding register name: ssc_tshr access type : read/write tsdat: transmit synchronization data right aligned regardless of the number of data bits defined by fslen in ssc_tfmr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rsdat 76543210 rsdat 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 tsdat 76543210 tsdat
342 at91sam7s64 preliminary 6070a?atarm?28-oct-04 ssc status register register name : ssc_sr access type : read-only txrdy: transmit ready 0: data has been loaded in ssc_thr and is waiting to be loaded in the transmit shift register. 1: ssc_thr is empty. txempty: transmit empty 0: data remains in ssc_thr or is currently transmitted from transmit shift register. 1: last data written in ssc_thr has been loaded in transmit shift register and transmitted by it. endtx: end of transmission 0: the register ssc_tcr has not reached 0 since the last write in ssc_tcr or ssc_tncr. 1: the register ssc_tcr has reached 0 since the last write in ssc_tcr or ssc_tncr. txbufe: transmit buffer empty 0: ssc_tcr or ssc_tncr have a value other than 0. 1: both ssc_tcr and ssc_tncr have a value of 0. rxrdy: receive ready 0: ssc_rhr is empty. 1: data has been received and loaded in ssc_rhr. ovrun: receive overrun 0: no data has been loaded in ssc_rhr while previous data has not been read since the last read of the status register. 1: data has been loaded in ssc_rhr while previous data has not yet been read since the last read of the status register. endrx: end of reception 0: data is written on the receive counter register or receive next counter register. 1: end of pdc transfer when receive counter register has arrived at zero. rxbuff: receive buffer full 0: ssc_rcr or ssc_rncr have a value other than 0. 1: both ssc_rcr and ssc_rncr have a value of 0. txsyn: transmit sync 0: a tx sync has not occurred since the last read of the status register. 1: a tx sync has occurred since the last read of the status register. rxsyn: receive sync 0: a rx sync has not occurred since the last read of the status register. 1: a rx sync has occurred since the last read of the status register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ??????rxentxen 15 14 13 12 11 10 9 8 ????r xsyn txsyn ? ? 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy
343 at91sam7s64 preliminary 6070a?atarm?28-oct-04 txen: transmit enable 0: transmit data is disabled. 1: transmit data is enabled. rxen: receive enable 0: receive data is disabled. 1: receive data is enabled.
344 at91sam7s64 preliminary 6070a?atarm?28-oct-04 ssc interrupt enable register register name : ssc_ier access type : write-only txrdy: transmit ready txempty: transmit empty endtx: end of transmission txbufe: transmit buffer empty rxrdy: receive ready ovrun: receive overrun endrx: end of reception rxbuff: receive buffer full txsyn: tx sync rxsyn: rx sync 0: no effect. 1: enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????r xsyn txsyn ? ? 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy
345 at91sam7s64 preliminary 6070a?atarm?28-oct-04 ssc interrupt disable register register name : ssc_idr access type : write-only txrdy: transmit ready txempty: transmit empty endtx: end of transmission txbufe: transmit buffer empty rxrdy: receive ready ovrun: receive overrun endrx: end of reception rxbuff: receive buffer full txsyn: tx sync rxsyn: rx sync 0: no effect. 1: disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????r xsyn txsyn ? ? 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy
346 at91sam7s64 preliminary 6070a?atarm?28-oct-04 ssc interrupt mask register register name : ssc_imr access type : read-only txrdy: transmit ready txempty: transmit empty endtx: end of transmission txbufe: transmit buffer empty rxrdy: receive ready ovrun: receive overrun endrx: end of reception rxbuff: receive buffer full txsyn: tx sync rxsyn: rx sync 0: the corresponding interrupt is disabled. 1: the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????r xsyn txsyn ? ? 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy
347 at91sam7s64 preliminary 6070a?atarm?28-oct-04 timer/counter (tc) overview the timer/counter (tc) includes three identical 16-bit timer/counter channels. each channel can be independently programmed to perform a wide range of functions includ- ing frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user. each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. the timer/counter block has two global registers which act upon all three tc channels. the block control register allows the three channels to be started simultaneously with the same instruction. the block mode register defines the external clock inputs for each channel, allowing them to be chained. block diagram figure 149. timer/counter block diagram timer/counter channel 0 timer/counter channel 1 timer/counter channel 2 sync parallel i/o controller tc1xc1s tc0xc0s tc2xc2s int0 int1 int2 tioa0 tioa1 tioa2 tiob0 tiob1 tiob2 xc0 xc1 xc2 xc0 xc1 xc2 xc0 xc1 xc2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tioa1 tioa2 tioa0 tioa2 tioa0 tioa1 advanced interrupt controller tclk0 tclk1 tclk2 tioa0 tiob0 tioa1 tiob1 tioa2 tiob2 timer counter tioa tiob tioa tiob tioa tiob sync sync timer_clock2 timer_clock3 timer_clock4 timer_clock5 timer_clock1
348 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pin name list product dependencies i/o lines the pins used for interfacing the compliant external devices may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the tc pins to their peripheral functions. power management the tc is clocked through the power management controller (pmc), thus the programmer must first configure the pmc to enable the timer/counter clock. interrupt the tc has an interrupt line connected to the advanced interrupt controller (aic). handling the tc interrupt requires programming the aic before configuring the tc. functional description tc description the three channels of the timer/counter are independent and identical in operation. the reg- isters for channel programming are listed in table 77 on page 360. 16-bit counter each channel is organized around a 16-bit counter. the value of the counter is incremented at each positive edge of the selected clock. when the counter has reached the value 0xffff and passes to 0x0000, an overflow occurs and the covfs bit in tc_sr (status register) is set. table 74. signal name description block/channel signal name description channel signal xc0, xc1, xc2 external clock inputs tioa capture mode: timer/counter input waveform mode: timer/counter output tiob capture mode: timer/counter input waveform mode: timer/counter input/output int interrupt signal output sync synchronization input signal table 75. tc pin list pin name description type tclk0-tclk2 external clock input input tioa0-tioa2 i/o line a i/o tiob0-tiob2 i/o line b i/o
349 at91sam7s64 preliminary 6070a?atarm?28-oct-04 the current value of the counter is accessible in real time by reading the counter value regis- ter, tc_cv. the counter can be reset by a trigger. in this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. clock selection at block level, input clock signals of each channel can either be connected to the external inputs tclk0, tclk1 or tclk2, or be connected to the configurable i/o signals tioa0, tioa1 or tioa2 for chaining by programming the tc_bmr (block mode). see figure 150. each channel can independently select an internal or external clock source for its counter: internal clock signals: timer_clock1, timer_clock2, timer_clock3, timer_clock4, timer_clock5 external clock signals: xc0, xc1 or xc2 this selection is made by the tcclks bits in the tc channel mode register. the selected clock can be inverted with the clki bit in tc_cmr. this allows counting on the opposite edges of the clock. the burst function allows the clock to be validated when an external signal is high. the burst parameter in the mode register defines this signal (none, xc0, xc1, xc2). note: in all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock period. the external clock frequency must be at least 2.5 times lower than the master clock figure 150. clock selection clock control the clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. see figure 151. the clock can be enabled or disabled by the user with the clken and the clkdis commands in the control register. in capture mode it can be disabled by an rb load event if ldbdis is set to 1 in tc_cmr. in waveform mode, it can be disabled by an rc compare event if cpcdis is set to 1 in tc_cmr. when disabled, the start or the stop actions have no effect: only a clken command in the control register can re-enable the clock. when the clock is enabled, the clksta bit is set in the status register. timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki burst 1 selected clock
350 at91sam7s64 preliminary 6070a?atarm?28-oct-04 the clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. the clock can be stopped by an rb load event in capture mode (ldbstop = 1 in tc_cmr) or a rc compare event in waveform mode (cpcstop = 1 in tc_cmr). the start and the stop commands have effect only if the clock is enabled. figure 151. clock control tc operating modes each channel can independently operate in two different modes: capture mode provides measurement on signals. waveform mode provides wave generation. the tc operating mode is programmed with the wave bit in the tc channel mode register. in capture mode, tioa and tiob are configured as inputs. in waveform mode, tioa is always configured to be an output and tiob is an output if it is not selected to be the external trigger. trigger a trigger resets the counter and starts the counter clock. three types of triggers are common to both modes, and a fourth external trigger is available to each mode. the following triggers are common to both modes: software trigger: each channel has a software trigger, available by setting swtrg in tc_ccr. sync: each channel has a synchronization signal sync. when asserted, this signal has the same effect as a software trigger. the sync signals of all channels are asserted simultaneously by writing tc_bcr (block control) with sync set. compare rc trigger: rc is implemented in each channel and can provide a trigger when the counter value matches the rc value if cpctrg is set in tc_cmr. the channel can also be configured to have an external trigger. in capture mode, the external trigger signal can be selected between tioa and tiob. in waveform mode, an external event can be programmed on one of the following signals: tiob, xc0, xc1 or xc2. this external event can then be programmed to perform a trigger by setting enetrg in tc_cmr. qs r s r q clksta clken clkdis stop event disable event counter clock selected clock trigger
351 at91sam7s64 preliminary 6070a?atarm?28-oct-04 if an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. this means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. capture operating mode this mode is entered by clearing the wave param eter in tc_cmr (channel mode register). capture mode allows the tc channel to perform measurements such as pulse timing, fre- quency, period, duty cycle and phase on tioa and tiob signals which are considered as inputs. figure 152 shows the configuration of the tc channel when programmed in capture mode. capture registers a and b registers a and b (ra and rb) are used as capture registers. this means that they can be loaded with the counter value when a programmable event occurs on the signal tioa. the ldra parameter in tc_cmr defines the tioa edge for the loading of register a, and the ldrb parameter defines the tioa edge for the loading of register b. ra is loaded only if it has not been loaded since the last trigger or if rb has been loaded since the last loading of ra. rb is loaded only if ra has been loaded since the last trigger or the last loading of rb. loading ra or rb before the read of the last value loaded sets the overrun error flag (lovrs) in tc_sr (status register). in this case, the old value is overwritten. trigger conditions in addition to the sync signal, the software trigger and the rc compare trigger, an external trigger can be defined. the abetrg bit in tc_cmr selects tioa or tiob input signal as an external trigger. the etrgedg parameter defines the edge (rising, falling or both) detected to generate an exter- nal trigger. if etrgedg = 0 (none), the external trigger is disabled.
352 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 152. capture mode timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki qs r s r q clksta clken clkdis burst tiob register c capture register a capture register b compare rc = 16-bit counter abetrg swtrg etrgedg cpctrg tc1_imr trig ldrbs ldras etrgs tc1_sr lovrs covfs sync 1 mtiob tioa mtioa ldra ldbstop if ra is not loaded or rb is loaded if ra is loaded ldbdis cpcs int edge detector edge detector ldrb edge detector clk ovf reset timer/counter channel
353 at91sam7s64 preliminary 6070a?atarm?28-oct-04 waveform operating mode waveform operating mode is entered by setting the wave parameter in tc_cmr (channel mode register). in waveform operating mode the tc channel generates 1 or 2 pwm signals with the same frequency and independently programmable duty cycles, or generates different types of one- shot or repetitive pulses. in this mode, tioa is configured as an output and tiob is defined as an output if it is not used as an external event (eevt parameter in tc_cmr). figure 153 shows the configuration of the tc channel when programmed in waveform oper- ating mode. waveform selection depending on the wavsel parameter in tc_c mr (channel mode register), the behavior of tc_cv varies. with any selection, ra, rb and rc can all be used as compare registers. ra compare is used to control the tioa output, rb compare is used to control the tiob out- put (if correctly configured) and rc compare is used to control tioa and/or tiob outputs.
354 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 153. waveform mode tcclks clki qs r s r q clksta clken clkdis cpcdis burst tiob register a register b register c compare ra = compare rb = compare rc = cpcstop 16-bit counter eevt eevtedg sync swtrg enetrg wavsel tc1_imr trig acpc acpa aeevt aswtrg bcpc bcpb beevt bswtrg tioa mtioa tiob mtiob cpas covfs etrgs tc1_sr cpcs cpbs clk ovf reset output controller output controller int 1 edge detector timer/counter channel timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 wavsel
355 at91sam7s64 preliminary 6070a?atarm?28-oct-04 wavsel = 00 when wavsel = 00, the value of tc_cv is incremented from 0 to 0xffff. once 0xffff has been reached, the value of tc_cv is reset. incrementation of tc_cv starts again and the cycle continues. see figure 154. an external event trigger or a software trigger can reset the value of tc_cv. it is important to note that the trigger may occur at any time. see figure 155. rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (cpcstop = 1 in tc_cmr) and/or disable the counter clock (cpcdis = 1 in tc_cmr). figure 154. wavsel= 00 without trigger figure 155. wavsel= 00 with trigger time counter value r c r b r a tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples time counter value r c r b r a tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples counter cleared by trigger
356 at91sam7s64 preliminary 6070a?atarm?28-oct-04 wavsel = 10 when wavsel = 10, the value of tc_cv is incremented from 0 to the value of rc, t hen auto- matically reset on a rc compare. once the value of tc_cv has been reset, it is then incremented and so on. see figure 156. it is important to note that tc_cv can be reset at any time by an external event or a software trigger if both are programmed correctly. see figure 157. in addition, rc compare can stop the counter clock (cpcstop = 1 in tc_cmr) and/or dis- able the counter clock (cpcdis = 1 in tc_cmr). figure 156. wavsel = 10 without trigger figure 157. wavsel = 10 with trigger time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples counter cleared by trigger
357 at91sam7s64 preliminary 6070a?atarm?28-oct-04 wavsel = 01 when wavsel = 01, the value of tc_cv is incremented from 0 to 0xffff. once 0xffff is reached, the value of tc_cv is decremented to 0, then re-incremented to 0xffff and so on. see figure 158. a trigger such as an external event or a software trigger can modify tc_cv at any time. if a trigger occurs while tc_cv is incrementing, tc_cv then decrements. if a trigger is received while tc_cv is decrementing, tc_cv then increments. see figure 159. rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (cpcstop = 1) and/or disable the counter clock (cpcdis = 1). figure 158. wavsel = 01 without tri gger figure 159. wavsel = 01 with tri gger time counter value r c r b r a tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a
358 at91sam7s64 preliminary 6070a?atarm?28-oct-04 wavsel = 11 when wavsel = 11, the value of tc_cv is incremented from 0 to rc. once rc is reached, the value of tc_cv is decremented to 0, then re-incremented to rc and so on. see figure 160. a trigger such as an external event or a software trigger can modify tc_cv at any time. if a trigger occurs while tc_cv is incrementing, tc_cv then decrements. if a trigger is received while tc_cv is decrementing, tc_cv then increments. see figure 161. rc compare can stop the counter clock (cpcstop = 1) and/or disable the counter clock (cpcdis = 1). figure 160. wavsel = 11 without tri gger figure 161. wavsel = 11 with tri gger time counter value r c r b r a tiob tioa counter decremented by compare match with rc 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with rc 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a
359 at91sam7s64 preliminary 6070a?atarm?28-oct-04 external event/trigger conditions an external event can be programmed to be detected on one of the clock sources (xc0, xc1, xc2) or tiob. the external event selected can then be used as a trigger. the parameter eevt parameter in tc_cmr selects the external trigger. the eevtedg parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). if eevtedg is cleared (none), no external event is defined. if tiob is defined as an external event signal ( eevt = 0), tiob is no longer used as an output and the tc channel can only generate a waveform on tioa. when an external event is defined, it can be used as a trigger by setting bit enetrg in tc_cmr. as in capture mode, the sync signal and the software trigger are also available as triggers. rc compare can also be used as a trigger depending on the parameter wavsel. output controller the output controller defines the output level changes on tioa and tiob following an event. tiob control is used only if tiob is defined as output (not as an external event). the following events control tioa and tiob: software trigger, external event and rc com- pare. ra compare controls tioa and rb compare controls tiob. each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in tc_cmr.
360 at91sam7s64 preliminary 6070a?atarm?28-oct-04 timer/counter (tc) user interface global register mapping tc_bcr (block control register) and tc_bmr (block mode register) control the whole tc block. tc channels are controlled by the registers listed in table 77 . the offset of each of the channel registers in table 77 is in relation to the offset of the corresponding channel as men- tioned in table 77 . channel memory mapping note: 1. read only if wave = 0 table 76. timer/counter (tc) global register map offset channel/register name access reset value 0x00 tc channel 0 see table 77 0x40 tc channel 1 see table 77 0x80 tc channel 2 see table 77 0xc0 tc block control register tc_bcr write-only ? 0xc4 tc block mode register tc_bmr read/write 0 table 77. timer/counter (tc) channel memory mapping offset register name access reset value 0x00 channel control register tc_ccr write-only ? 0x04 channel mode register tc_cmr read/write 0 0x08 reserved ? ? ? 0x0c reserved ? ? ? 0x10 counter value tc_cv read-only 0 0x14 register a tc_ra read/write (1) 0 0x18 register b tc_rb read/write (1) 0 0x1c register c tc_rc read/write 0 0x20 status register tc_sr read-only 0 0x24 interrupt enable register tc_ier write-only ? 0x28 interrupt disable register tc_idr write-only ? 0x2c interrupt mask register tc_imr read-only 0 0x30-0xfc reserved ? ? ?
361 at91sam7s64 preliminary 6070a?atarm?28-oct-04 tc block control register register name: tc_bcr access type: write-only sync: synchro command 0 = no effect. 1 = asserts the sync signal which generates a software trigger simultaneously for each of the channels. tc block mode register register name: tc_bmr access type: read/write tc0xc0s: external clock signal 0 selection tc1xc1s: external clock signal 1 selection 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????sync 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? tc2xc2s tcxc1s tc0xc0s tc0xc0s signal connected to xc0 00tclk0 0 1 none 10tioa1 11tioa2 tc1xc1s signal connected to xc1 00tclk1 0 1 none 10tioa0 11tioa2
362 at91sam7s64 preliminary 6070a?atarm?28-oct-04 tc2xc2s: external clock signal 2 selection tc channel control register register name: tc_ccr access type: write-only clken: counter clock enable command 0 = no effect. 1 = enables the clock if clkdis is not 1. clkdis: counter clock disable command 0 = no effect. 1 = disables the clock. swtrg: software trigger command 0 = no effect. 1 = a software trigger is performed: the counter is reset and the clock is started. tc2xc2s signal connected to xc2 00tclk2 0 1 none 10tioa0 11tioa1 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? ? ? swtrg clkdis clken
363 at91sam7s64 preliminary 6070a?atarm?28-oct-04 tc channel mode register: capture mode register name: tc_cmr access type: read/write tcclks: clock selection clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. burst: burst signal selection ldbstop: counter clock stopped with rb loading 0 = counter clock is not stopped when rb loading occurs. 1 = counter clock is stopped when rb loading occurs. ldbdis: counter clock disable with rb loading 0 = counter clock is not disabled when rb loading occurs. 1 = counter clock is disabled when rb loading occurs. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? ? ldrb ldra 15 14 13 12 11 10 9 8 wave = 0 cpctrg ? ? ? abetrg etrgedg 76543210 ldbdis ldbstop burst clki tcclks tcclks clock selected 0 0 0 timer_clock1 0 0 1 timer_clock2 0 1 0 timer_clock3 0 1 1 timer_clock4 1 0 0 timer_clock5 101xc0 110xc1 111xc2 burst 0 0 the clock is not gated by an external signal. 0 1 xc0 is anded with the selected clock. 1 0 xc1 is anded with the selected clock. 1 1 xc2 is anded with the selected clock.
364 at91sam7s64 preliminary 6070a?atarm?28-oct-04 etrgedg: external trigger edge selection abetrg: tioa or tiob external trigger selection 0 = tiob is used as an external trigger. 1 = tioa is used as an external trigger. cpctrg: rc compare trigger enable 0 = rc compare has no effect on the counter and its clock. 1 = rc compare resets the counter and starts the counter clock. wave 0 = capture mode is enabled. 1 = capture mode is disabled (waveform mode is enabled). ldra: ra loading selection ldrb: rb loading selection etrgedg edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge ldra edge 0 0 none 0 1 rising edge of tioa 1 0 falling edge of tioa 1 1 each edge of tioa ldrb edge 0 0 none 0 1 rising edge of tioa 1 0 falling edge of tioa 1 1 each edge of tioa
365 at91sam7s64 preliminary 6070a?atarm?28-oct-04 tc channel mode register: waveform mode register name: tc_cmr access type: read/write tcclks: clock selection clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. burst: burst signal selection cpcstop: counter clock stopped with rc compare 0 = counter clock is not stopped when counter reaches rc. 1 = counter clock is stopped when counter reaches rc. cpcdis: counter clock disable with rc compare 0 = counter clock is not disabled when counter reaches rc. 1 = counter clock is disabled when counter reaches rc. 31 30 29 28 27 26 25 24 bswtrg beevt bcpc bcpb 23 22 21 20 19 18 17 16 aswtrg aeevt acpc acpa 15 14 13 12 11 10 9 8 wave = 1 wavsel enetrg eevt eevtedg 76543210 cpcdis cpcstop burst clki tcclks tcclks clock selected 0 0 0 timer_clock1 0 0 1 timer_clock2 0 1 0 timer_clock3 0 1 1 timer_clock4 1 0 0 timer_clock5 101xc0 110xc1 111xc2 burst 0 0 the clock is not gated by an external signal. 0 1 xc0 is anded with the selected clock. 1 0 xc1 is anded with the selected clock. 1 1 xc2 is anded with the selected clock.
366 at91sam7s64 preliminary 6070a?atarm?28-oct-04 eevtedg: external event edge selection eevt: external event selection note: 1. if tiob is chosen as the external event signal, it is configured as an input and no longer generates waveforms . enetrg: external event trigger enable 0 = the external event has no effect on the counter and its clock. in this case, the selected external event only controls the tioa output. 1 = the external event resets the counter and starts the counter clock. wavsel: waveform selection wave = 1 0 = waveform mode is disabled (capture mode is enabled). 1 = waveform mode is enabled. acpa: ra compare effect on tioa acpc: rc compare effect on tioa eevtedg edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge eevt signal selected as external event tiob direction 00tiob input (1) 0 1 xc0 output 1 0 xc1 output 1 1 xc2 output wavsel effect 0 0 up mode without automatic trigger on rc compare 1 0 up mode with automatic trigger on rc compare 0 1 updown mode without automatic trigger on rc compare 1 1 updown mode with automatic trigger on rc compare acpa effect 0 0 none 01set 1 0 clear 11toggle acpc effect 0 0 none 01set 1 0 clear 11toggle
367 at91sam7s64 preliminary 6070a?atarm?28-oct-04 aeevt: external event effect on tioa aswtrg: software trigger effect on tioa bcpb: rb compare effect on tiob bcpc: rc compare effect on tiob beevt: external event effect on tiob bswtrg: software trigger effect on tiob aeevt effect 0 0 none 01set 1 0 clear 11toggle aswtrg effect 0 0 none 01set 1 0 clear 11toggle bcpb effect 0 0 none 01set 1 0 clear 11toggle bcpc effect 0 0 none 01set 1 0 clear 11toggle beevt effect 0 0 none 01set 1 0 clear 11toggle bswtrg effect 0 0 none 01set 1 0 clear 11toggle
368 at91sam7s64 preliminary 6070a?atarm?28-oct-04 tc counter value register register name: tc_cv access type: read-only cv: counter value cv contains the counter value in real time. tc register a register name: tc_ra access type: read-only if wave = 0, read/write if wave = 1 ra: register a ra contains the register a value in real time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cv 76543210 cv 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ra 76543210 ra
369 at91sam7s64 preliminary 6070a?atarm?28-oct-04 tc register b register name: tc_rb access type: read-only if wave = 0, read/write if wave = 1 rb: register b rb contains the register b value in real time. tc register c register name: tc_rc access type: read/write rc: register c rc contains the register c value in real time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rb 76543210 rb 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rc 76543210 rc
370 at91sam7s64 preliminary 6070a?atarm?28-oct-04 tc status register register name: tc_sr access type: read-only covfs: counter overflow status 0 = no counter overflow has occurred since the last read of the status register. 1 = a counter overflow has occurred since the last read of the status register. lovrs: load overrun status 0 = load overrun has not occurred since the last read of the status register or wave = 1. 1 = ra or rb have been loaded at least twice without any read of the corresponding register since the last read of the sta- tus register, if wave = 0. cpas: ra compare status 0 = ra compare has not occurred since the last read of the status register or wave = 0. 1 = ra compare has occurred since the last read of the status register, if wave = 1. cpbs: rb compare status 0 = rb compare has not occurred since the last read of the status register or wave = 0. 1 = rb compare has occurred since the last read of the status register, if wave = 1. cpcs: rc compare status 0 = rc compare has not occurred since the last read of the status register. 1 = rc compare has occurred since the last read of the status register. ldras: ra loading status 0 = ra load has not occurred since the last read of the status register or wave = 1. 1 = ra load has occurred since the last read of the status register, if wave = 0. ldrbs: rb loading status 0 = rb load has not occurred since the last read of the status register or wave = 1. 1 = rb load has occurred since the last read of the status register, if wave = 0. etrgs: external trigger status 0 = external trigger has not occurred since the last read of the status register. 1 = external trigger has occurred since the last read of the status register. clksta: clock enabling status 0 = clock is disabled. 1 = clock is enabled. mtioa: tioa mirror 0 = tioa is low. if wave = 0, this means that tioa pin is low. if wave = 1, this means that tioa is driven low. 1 = tioa is high. if wave = 0, this means that tioa pin is high. if wave = 1, this means that tioa is driven high. mtiob: tiob mirror 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?????mtiobmtioaclksta 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
371 at91sam7s64 preliminary 6070a?atarm?28-oct-04 0 = tiob is low. if wave = 0, this means that tiob pin is low. if wave = 1, this means that tiob is driven low. 1 = tiob is high. if wave = 0, this means that tiob pin is high. if wave = 1, this means that tiob is driven high.
372 at91sam7s64 preliminary 6070a?atarm?28-oct-04 tc interrupt enable register register name: tc_ier access type: write-only covfs: counter overflow 0 = no effect. 1 = enables the counter overflow interrupt. lovrs: load overrun 0 = no effect. 1 = enables the load overrun interrupt. cpas: ra compare 0 = no effect. 1 = enables the ra compare interrupt. cpbs: rb compare 0 = no effect. 1 = enables the rb compare interrupt. cpcs: rc compare 0 = no effect. 1 = enables the rc compare interrupt. ldras: ra loading 0 = no effect. 1 = enables the ra load interrupt. ldrbs: rb loading 0 = no effect. 1 = enables the rb load interrupt. etrgs: external trigger 0 = no effect. 1 = enables the external trigger interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
373 at91sam7s64 preliminary 6070a?atarm?28-oct-04 tc interrupt disable register register name: tc_idr access type: write-only covfs: counter overflow 0 = no effect. 1 = disables the counter overflow interrupt. lovrs: load overrun 0 = no effect. 1 = disables the load overrun interrupt (if wave = 0). cpas: ra compare 0 = no effect. 1 = disables the ra compare interrupt (if wave = 1). cpbs: rb compare 0 = no effect. 1 = disables the rb compare interrupt (if wave = 1). cpcs: rc compare 0 = no effect. 1 = disables the rc compare interrupt. ldras: ra loading 0 = no effect. 1 = disables the ra load interrupt (if wave = 0). ldrbs: rb loading 0 = no effect. 1 = disables the rb load interrupt (if wave = 0). etrgs: external trigger 0 = no effect. 1 = disables the external trigger interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
374 at91sam7s64 preliminary 6070a?atarm?28-oct-04 tc interrupt mask register register name: tc_imr access type: read-only covfs: counter overflow 0 = the counter overflow interrupt is disabled. 1 = the counter overflow interrupt is enabled. lovrs: load overrun 0 = the load overrun interrupt is disabled. 1 = the load overrun interrupt is enabled. cpas: ra compare 0 = the ra compare interrupt is disabled. 1 = the ra compare interrupt is enabled. cpbs: rb compare 0 = the rb compare interrupt is disabled. 1 = the rb compare interrupt is enabled. cpcs: rc compare 0 = the rc compare interrupt is disabled. 1 = the rc compare interrupt is enabled. ldras: ra loading 0 = the load ra interrupt is disabled. 1 = the load ra interrupt is enabled. ldrbs: rb loading 0 = the load rb interrupt is disabled. 1 = the load rb interrupt is enabled. etrgs: external trigger 0 = the external trigger interrupt is disabled. 1 = the external trigger interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
375 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pulse width modulation controller (pwm) overview the pwm macrocell controls several channels independently. each channel controls one square output waveform. characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. each channel selects and uses one of the clocks provided by the clock generator. the cl ock generator provides several clo cks result- ing from the division of the pwm macrocell master clock. all pwm macrocell accesses are made through apb m apped registers. channels can be synchronized, to generate non overlapped waveforms. all channels integrate a double buffering system in order to prevent an unexpected output waveform while modifying the period or the duty-cycle. block diagram figure 162. pulse width modulation controller block diagram pwm controller apb pwmx pwmx pwmx channel update duty cycle counter pwm0 channel pio aic pmc mck clock generator apb interface interrupt generator clock selector period comparator update duty cycle counter clock selector period comparator pwm0 pwm0
376 at91sam7s64 preliminary 6070a?atarm?28-oct-04 i/o lines description each channel outputs one waveform on one external i/o line. product dependencies i/o lines the pins used for interfacing the pwm may be multiplexed with pio lines. the programmer must first program the pio controller to assign the desired pwm pins to their peripheral func- tion. if i/o lines of the pwm are not used by the application, they can be used for other purposes by the pio controller. all of the pwm outputs may or may not be enabled. if an application requires only four chan- nels, then only four pio lines will be assigned to pwm outputs. power management the pwm is not continuously clocked. the programmer must first enable the pwm clock in the power management controller (pmc) before using the pwm. however, if the application does not require pwm operations, the pwm clock can be stopped when not needed and be restarted later. in this case, the pwm w ill resume its operations where it left off. configuring the pwm does not require the pwm clock to be enabled. interrupt sources the pwm interrupt line is connected on one of the internal sources of the advanced interrupt controller. using the pwm interrupt requires the aic to be programmed first. note that it is not recommended to use the pwm interrupt line in edge sensitive mode. table 78. i/o line description name description type pwmx pwm waveform output for channel x output
377 at91sam7s64 preliminary 6070a?atarm?28-oct-04 functional description the pwm macrocell is primarily composed of a clock generator module and 4 channels. ? clocked by the system clock, mck, the clock generator module provides 13 clocks. ? each channel can independently choose one of the clock generator outputs. ? each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. pwm clock generator figure 163. functional view of the clock generator block diagram caution: before using the pwm macrocell, the programmer must first enable the pwm clock in the power management controller (pmc). the pwm macrocell master clock, mck, is divided in the clock generator module to provide different clocks available for all channels. each channel can independently select one of the divided clocks. the clock generator is divided in three blocks: ? a modulo n counter which provides 11 clocks: f mck , f mck /2, f mck /4, f mck /8, f mck /16, f mck /32, f mck /64, f mck /128, f mck /256, f mck /512, f mck /1024 ? two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clka and clkb each linear divider can independently divide one of the clocks of the modulo n counter. the selection of the clock to be divided is made according to the prea (preb) field of the pwm modulo n counter mck mck/2 mck/4 mck/16 mck/32 mck/64 mck/8 divider a clka diva pwm_mr mck mck/128 mck/256 mck/512 mck/1024 prea divider b clkb divb pwm_mr preb
378 at91sam7s64 preliminary 6070a?atarm?28-oct-04 mode register (pwm_mr). the resulting clock clka (clkb) is the clock selected divided by diva (divb) field value in the pwm mode register (pwm_mr). after a reset of the pwm controller, diva (divb) and prea (preb) in the pwm mode regis- ter are set to 0. this implies that after reset clka (clkb) are turned off. at reset, all clocks provided by the modulo n counter are turned off except clock ?clk?. this sit- uation is also true when the pwm master clock is turned off through the power management controller. pwm channel block diagram figure 164. functional view of the channel block diagram each of the 4 channels is composed of three blocks: a clock selector which selects one of the clocks provided by the clock generator described in section ?pwm clock generator? on page 377. an internal counter clocked by the output of the clock selector. this internal counter is incremented or decremented according to the channel configuration and comparators events. the size of the internal counter is 16 bits. a comparator used to generate events according to the internal counter value. it also computes the pwmx output waveform according to the configuration. waveform properties the different properties of output waveforms are: the internal clock selection . the internal channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. this channel parameter is defined in the cpre field of the pwm_cmrx register. this field is reset at 0. the waveform period . this channel parameter is defined in the cprd field of the pwm_cprdx register. - if the waveform is left aligned, then the output waveform period depends on the counter source clock and can be claculated: by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be: by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or if the waveform is center aligned then the output waveform period depends on the counter source clock and can be calculated: comparator pwmx output waveform internal counter clock selector channel inputs from clock generator inputs from apb bus x cprd () mck ------------------------------- crpd diva () mck ------------------------------------------ crpd divab () mck ----------------------------------------------
379 at91sam7s64 preliminary 6070a?atarm?28-oct-04 by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). the resulting period formula will be: by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or the waveform duty cycle . this channel parameter is defined in the cdty field of the pwm_cdtyx register. if the waveform is left aligned then: if the waveform is center aligned, then: the waveform polarity. at the beginning of the period, the signal can be at high or low level. this property is defined in the cpol field of the pwm_cmrx register. by default the signal starts by a low level. the waveform alignment . the output waveform can be left or center aligned. center aligned waveforms can be used to generate non overlapped waveforms. this property is defined in the calg field of the pwm_cmrx register. the default mode is left aligned. figure 165. non overlapped center aligned waveforms note: 1. see figure 166 on page 381 for a detailed description of center aligned waveforms. when center aligned, the internal channel counter increases up to cprd and .decreases down to 0. this ends the period. when left aligned, the internal channel counter increases up to cprd and is reset. this ends the period. thus, for the same cprd value, the period for a center aligned channel is twice the period for a left aligned channel. waveforms are fixed at 0 when: cdty = cprd and cpol = 0 2 x cprd () mck ---------------------------------------- - 2 cprd diva () mck --------------------------------------------------- - 2 cprd divb () mck --------------------------------------------------- - duty cycle period 1 fchannel_x_clock cdty ? ? () period ------------------------------------------------------------------------------------------------------- - = duty cycle period 2 ? () 1 fchannel_x_clock cdty ? ? ()) period 2 ? () ---------------------------------------------------------------------------------------------------------------------- - = pwm0 pwm1 period no overlap
380 at91sam7s64 preliminary 6070a?atarm?28-oct-04 cdty = 0 and cpol = 1 waveforms are fixed at 1 (once the channel is enabled) when: cdty = 0 and cpol = 0 cdty = cprd and cpol = 1 the waveform polarity must be set before enabling the channel. this immediately affects the channel output level. changes on channel polarity are not taken into account while the chan- nel is enabled.
381 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 166. waveform properties pwm_mckx chidx(pwm_sr) center aligned cprd(pwm_cprdx) cdty(pwm_cdtyx) pwm_ccntx output waveform pwmx cpol(pwm_cmrx) = 0 output waveform pwmx cpol(pwm_cmrx) = 1 chidx(pwm_isr) left aligned cprd(pwm_cprdx) cdty(pwm_cdtyx) pwm_ccntx output waveform pwmx cpol(pwm_cmrx) = 0 output waveform pwmx cpol(pwm_cmrx) = 1 chidx(pwm_isr) calg(pwm_cmrx) = 0 calg(pwm_cmrx) = 1 period period chidx(pwm_ena) chidx(pwm_dis)
382 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pwm controller operations initialization before enabling the output channel, this channel must have been configured by the software application: configuration of the clock generator if diva and divb are required selection of the clock for each channel (cpre field in the pwm_cmrx register) configuration of the waveform alignment for each channel (calg field in the pwm_cmrx register) configuration of the period for each channel (cprd in the pwm_cprdx register). writing in pwm_cprdx register is possible while the channel is disabled. after validation of the channel, the user must use pwm_cupdx register to update pwm_cprdx as explained below. configuration of the duty cycle for each channel (cdty in the pwm_cdtyx register). writing in pwm_cdtyx register is possible while the channel is disabled. after validation of the channel, the user must use pwm_cupdx register to update pwm_cdtyx as explained below. configuration of the output waveform polarity for each channel (cpol in the pwm_cmrx register) enable interrupts (writing chidx in the pwm_ier register) enable the pwm channel (writing chidx in the pwm_ena register) it is possible to synchronize different channels by enabling them at the same time by means of writing simultaneously several chidx bits in the pwm_ena register. in such a situation, all channels may have the same clock selector configuration and the same period specified. source clock selection criteria the large number of source clocks can make se lection difficult. the relationship between the value in the period register (pwm_cprdx) and the duty cycle register (pwm_cdtyx) can help the user in choosing. the event number written in the period register gives the pwm accuracy. the duty cycle quantum cannot be lower than 1/pwm_cprdx value. the higher the value of pwm_cprdx, the greater the pwm accuracy. for example, if the user sets 15 (in decimal) in pwm_cprdx, the user is able to set a value between 1 up to 14 in pwm_cdtyx register. the resulting duty cycle quantum cannot be lower than 1/15 of the pwm period. changing the duty cycle or the period it is possible to modulate the output waveform duty cycle or period. to prevent an unexpected output waveform when modifying the waveform parameters while the channel is still enabled, pwm_cprdx and pwm_cdtyx registers are double buffered. the user can write a new period value or duty cycle value in the update register (pwm_cupdx). this register holds the new value until the end of the current cycle and updates the value for the next cycle. according to the cpd field in the pwm_cmrx register, pwm_cupdx either updates the pwm_cprdx or pwm_cdtyx.
383 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 167. synchronized period or duty cycle update to prevent overwriting the pwm_cupdx by software, the user can use status events in order to synchronize his software. two methods are possible. in both, the user must enable the ded- icated interrupt in pwm_ier at pwm controller level. the first method (polling method) consists of reading the relevant status bit in pwm_isr reg- ister according to the enabled channel(s). see figure 168. the second method uses an interrupt service routine associated with the pwm channel. note: reading the pwm_isr register automatically clears chidx flags. figure 168. polling method pwm_cupdx value pwm_cprdx pwm_cdtyx end of cycle pwm_cmrx. cpd user's writing 1 0 writing in pwm_cupdx the last write has been taken into account chidx = 1 writing in cpd field update of the period or duty cycle pwm_isr read acknowledgement and clear previous register state yes
384 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pwm user interface pwm register mapping note: 1. values in the version register vary with the version of the ip block implementation. table 79. pwm controller registers offset register name access peripheral reset value 0x00 pwm mode register pwm_mr read/write 0 0x04 pwm enable register pwm_ena write-only - 0x08 pwm disable register pwm_dis write-only - 0x0c pwm status register pwm_sr read-only 0 0x10 pwm interrupt enable register pwm_ier write-only - 0x14 pwm interrupt disable register pwm_idr write-only - 0x18 pwm interrupt mask register pwm_imr read-only 0 0x1c pwm interrupt status register pwm_isr read-only 0 0x4c - 0xf8 reserved ? ? ? 0xfc version register pwm_version read-only 0x- (1) 0x100 - 0x1fc reserved 0x200 channel 0 mode register pwm_cmr0 read/write 0x0 0x204 channel 0 duty cycle register pwm_cdty0 read/write 0x0 0x208 channel 0 period register pwm_cprd0 read/write 0x0 0x20c channel 0 counter register pwm_ccnt0 read-only 0x0 0x210 channel 0 update register pwm_cupd0 write-only - ... reserved 0x220 channel 1 mode register pwm_cmr1 read/write 0x0 0x224 channel 1 duty cycle register pwm_cdty1 read/write 0x0 0x228 channel 1 period register pwm_cprd1 read/write 0x0 0x22c channel 1 counter register pwm_ccnt1 read-only 0x0 0x230 channel 1 update register pwm_cupd1 write-only - ... ... ... ... ...
385 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pwm mode register register name: pwm_mr access type: read/write diva, divb: clka, clkb divide factor prea, preb 31 30 29 28 27 26 25 24 ???? preb 23 22 21 20 19 18 17 16 divb 15 14 13 12 11 10 9 8 ???? prea 76543210 diva diva, divb clka, clkb 0 clka, clkb clock is turned off 1 clka, clkb clock is clock selected by prea, preb 2-255 clka, clkb clock is clock selected by prea, preb divided by diva, divb factor. prea, preb divider input clock 0000mck. 0001mck/2 0010mck/4 0011mck/8 0100mck/16 0101mck/32 0110mck/64 0111mck/128 1000mck/256 1001mck/512 1010mck/ 1024 other reserved
386 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pwm enable register register name: pwm_ena access type: write-only chidx: channel id 0 = no effect. 1 = enable pwm output for channel x. pwm disable register register name: pwm_dis access type: write-only chidx: channel id 0 = no effect. 1 = disable pwm output for channel x. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
387 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pwm status register register name: pwm_sr access type: read-only chidx: channel id 0 = pwm output for channel x is disabled. 1 = pwm output for channel x is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
388 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pwm interrupt enable register register name: pwm_ier access type: write-only chidx: channel id. 0 = no effect. 1 = enable interrupt for pwm channel x. pwm interrupt disable register register name: pwm_idr access type: write-only chidx: channel id. 0 = no effect. 1 = disable interrupt for pwm channel x. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
389 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pwm interrupt mask register register name: pwm_imr access type: read-only chidx: channel id. 0 = interrupt for pwm channel x is disabled. 1 = interrupt for pwm channel x is enabled. pwm interrupt status register register name: pwm_isr access type: read-only chidx: channel id 0 = no new channel period has been achieved since the last read of the pwm_isr register. 1 = at least one new channel period has been achieved since the last read of the pwm_isr register. note: reading pwm_isr automatically clears chidx flags. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????chid3chid2chid1chid0
390 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pwm channel mode register register name: pwm_cmrx access type: read/write cpre: channel pre-scaler calg: channel alignment 0 = the period is left aligned. 1 = the period is center aligned. cpol: channel polarity 0 = the output waveform starts at a low level. 1 = the output waveform starts at a high level. cpd: channel update period 0 = writing to the pwm_cupdx will modify the duty cycle at the next period start event. 1 = writing to the pwm_cupdx will modify the period at the next period start event. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????cpdcpolcalg 76543210 ???? cpre cpre channel pre-scaler 0000mck 0001mck/2 0010mck/4 0011mck/8 0100mck/16 0101mck/32 0110mck/64 0111mck/128 1000mck/256 1001mck/512 1 0 1 0 mck/1024 1011clka 1100clkb other reserved
391 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pwm channel duty cycle register register name: pwm_ cdty x access type: read/write only the first 16 bits (internal channel counter size) are significative. cdty: channel duty cycle defines the waveform duty cycle. this value must be defined between 0 and cprd (pwm_cprx). 31 30 29 28 27 26 25 24 cdty 23 22 21 20 19 18 17 16 cdty 15 14 13 12 11 10 9 8 cdty 76543210 cdty
392 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pwm channel period register register name: pwm_cprdx access type: read/write only the first 16 bits (internal channel counter size) are significative. cprd: channel period if the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be calculated: ? by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). the result ing period formula will be: ? by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or if the waveform is center-aligned, then the output waveform period depends on the counter source clockand can be calculated: ? by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). the resu lting period formula will be: ? by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or 31 30 29 28 27 26 25 24 cprd 23 22 21 20 19 18 17 16 cprd 15 14 13 12 11 10 9 8 cprd 76543210 cprd x cprd () mck ------------------------------- crpd diva () mck ------------------------------------------ crpd divab () mck ---------------------------------------------- 2 x cprd () mck ---------------------------------------- - 2 cprd diva () mck --------------------------------------------------- - 2 cprd divb () mck --------------------------------------------------- -
393 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pwm channel counter register register name: pwm_ccntx access type: read-only cnt: channel counter register internal counter value. this register is reset when: the channel is enabled (writing chidx in the pwm_ena register). the counter reaches cprd value defined in the pwm_cprdx register if the waveform is left aligned. pwm channel update register register name: pwm_cupdx access type: write-only this register acts as a double buffer for the period or t he duty cycle. this prevents an unexpected waveform when modify- ing the waveform period or duty-cycle. only the first 16 bits (internal channel counter size) are significative. 31 30 29 28 27 26 25 24 cnt 23 22 21 20 19 18 17 16 cnt 15 14 13 12 11 10 9 8 cnt 76543210 cnt 31 30 29 28 27 26 25 24 cupd 23 22 21 20 19 18 17 16 cupd 15 14 13 12 11 10 9 8 cupd 76543210 cupd cpd (pwm_cmrx register) 0 the duty-cycle (cdtc in the pwm_cdrx register) is updated with the cupd value at the beginning of the next period. 1 the period (cprd in the pwm_cprx register) is updated with the cupd value at the beginning of the next period.
394 at91sam7s64 preliminary 6070a?atarm?28-oct-04 pwm version register register name: pwm_version access type: read-only version reserved. value subject to change. no functionality associated. this is the atmel internal version of the macrocell. mfn reserved. value subject to change. no functionality associated. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????? mfn 15 14 13 12 11 10 9 8 ???? version 76543210 version
395 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usb device port (udp) overview the usb device port (udp) is compliant with the universal serial bus (usb) v2.0 full-speed device specification. each endpoint can be configured in one several usb transfer types. it can be associated with one or two banks of a dual-port ram used to store the current data payload. if two banks are used, one dpr bank is read or written by the processor, while the other is read or written by the usb device peripheral. this feature is mandatory for isochronous endpoints. thus the device maintains the maximum bandwidth (1m bytes/s) by working with endpoints with two banks of dpr. suspend and resume are automatically detected by the usb device, which notifies the pro- cessor by raising an interrupt. depending on the product, an external signal can be used to send a wake-up to the usb host controller. block diagram figure 169. block diagram table 80. usb endpoint description endpoint number mnemonic dual-bank max. endpoint size endpoint type 0 ep0 no 8 control/bulk/interrupt 1 ep1 yes 64 bulk/iso/interrupt 3 ep2 yes 64 bulk/iso/interrupt 3 ep3 no 64 control/bulk/interrupt atmel bridge 12 mhz suspend/resume logic w r a p p e r w r a p p e r u s e r i n t e r f a c e serial interface engine sie mck master clock domain dual port ram fifo udpck recovered 12 mhz domain udp_int usb device embedded usb transceiver dp dm external_resume apb to mcu bus txoen eopn txd rxdm rxd rxdp
396 at91sam7s64 preliminary 6070a?atarm?28-oct-04 access to the udp is via the apb bus interface. read and write to the data fifo are done by reading and writing 8-bit values to apb registers. the udp peripheral requires two clocks: one peripheral clock used by the mck domain and a 48 mhz clock used by the 12 mhz domain. a usb 2.0 full-speed pad is embedded and controlled by the serial interface engine (sie). the signal external_resume is optional. it allo ws the udp peripheral to wake-up once in sys- tem mode. the host is then notified that the device asks for a resume. this optional feature must be also negotiated with the host during the enumeration. product dependencies for further details on the usb device hardware implementation, see ?usb device port? on page 28. the usb physical transceiver is integrated into the product. the bidirectional differential sig- nals dp and dm are available from the product boundary. two i/o lines may be used by the application: one to check that vbus is still available from the host. self-powered devices may use this entry to be notified that the host has been powered off. in this case, the board pull-up on dp must be disabled in order to prevent feeding current to the host. one to control the board pull-up on dp. thus, when the device is ready to communicate with the host, it activates its dp pull-up through this control line. i/o lines dp and dm are not controlled by any pio controllers. the embedded usb physical trans- ceiver is controlled by the usb device peripheral. to reserve an i/o line to check vbus, the programmer must first program the pio controller to assign this i/o in input pio mode. to reserve an i/o line to control the board pull-up, the programmer must first program the pio controller to assign this i/o in output pio mode. power management the usb device peripheral requires a 48 mhz clock. this clock must be generated by a pll with an accuracy of 0.25%. thus, the usb device receives two clocks from the power management controller (pmc): the master clock, mck, used to drive the peripheral user interface, and the udpck, used to inter- face with the bus usb signals (recovered 12 mhz domain). interrupt the usb device interface has an interrupt line connected to the advanced interrupt controller (aic). handling the usb device interrupt requires pr ogramming the aic before configuring the udp.
397 at91sam7s64 preliminary 6070a?atarm?28-oct-04 typical connection figure 170. board schematic to interface usb device peripheral usb_cnx is an input signal used to check if the host is connected usb_dp_pup is an output signal used to enable pull-up on dp. figure 170 shows automatic activation of pull-up after reset. 3v3 15 pf 15 pf 27 ? 33 pf 1.5 k ? 47 k ? 100 nf dm dp pan pam system reset 15 k ? 22 k ? 27 ? type b connector 1 2 34 usb_cnx usb_dp_pup
398 at91sam7s64 preliminary 6070a?atarm?28-oct-04 functional description usb v2.0 full- speed introduction the usb v2.0 full-speed provides communication services between host and attached usb devices. each device is offered with a collection of communication flows (pipes) associated with each endpoint. software on the host communicates with an usb device through a set of communication flows. figure 171. example of usb v2.0 full-speed communication control usb v2.0 full-speed transfer types a communication flow is carried over one of four transfer types defined by the usb device. usb bus transactions each transfer results in one or more transactions over the usb bus. there are five kinds of transactions flowing across the bus in packets: 1. setup transaction 2. data in transaction 3. data out transaction 4. status in transaction 5. status out transaction ep0 usb host v2.0 software client 1 software client 2 data flow: bulk out transfer data flow: bulk in transfer data flow: control transfer data flow: control transfer ep1 ep2 usb device 2.0 block 1 usb device 2.0 block 2 ep5 ep4 ep0 data flow: isochronous in transfer data flow: isochronous out transfer table 81. usb communication flow transfer direction bandwidth endpoint size error detection retrying control bi-directional not guaranteed 8, 16, 32, 64 yes automatic isochronous uni-directional guaranteed 1 - 1023 yes no interrupt uni-directional not guaranteed 64 yes yes bulk uni-directional not guaranteed 8, 16, 32, 64 yes yes
399 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usb transfer event definitions as indicated below, transfers are sequential events carried out on the usb bus. notes: 1. control transfer must use endpoints with no ping-pong attributes. 2. isochronous transfers must use endpoints with ping-pong attributes. 3. control transfers can be aborted using a stall handshake. handling transactions with usb v2.0 device peripheral setup transaction setup is a special type of host-to-device transaction used during control transfers. control transfers must be performed using endpoints with no ping-pong attributes. a setup transaction needs to be handled as soon as possible by the firmware. it is used to transmit requests from the host to the device. these requests are then handled by the usb device and may require more arguments. the arguments are sent to the device by a data out transaction which fol- lows the setup transaction. these requests may also return data. the data is carried out to the host by the next data in transaction which follows the setup transaction. a status transaction ends the control transfer. when a setup transfer is received by the usb endpoint: the usb device automatically acknowledges the setup packet rxsetup is set in the usb_csrx register an endpoint interrupt is generated while the r xsetup is not cleared. this interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. thus, firmware must detect the rxsetup polling the usb_csrx or catching an interrupt, read the setup packet in the fifo, then clear the rxsetup. rxsetup cannot be cleared before the setup packet has been read in the fifo. otherwise, the usb device would accept the next data out transfer and overwrite the setup packet in the fifo. table 82. usb transfer events control transfers (1) (3) setup transaction > data in transactions > status out transaction setup transaction > data out transactions > status in transaction setup transaction > status in transaction interrupt in transfer (device toward host) data in transaction > data in transaction interrupt out transfer (host toward device) data out transaction > data out transaction isochronous in transfer (2) (device toward host) data in transaction > data in transaction isochronous out transfer (2) (host toward device) data out transaction > data out transaction bulk in transfer (device toward host) data in transaction > data in transaction bulk out transfer (host toward device) data out transaction > data out transaction
400 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 172. setup transaction followed by a data out transaction data in transaction data in transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the device to the host. data in transactions in isochronous transfer must be done using endpoints with ping-pong attributes. using endpoints without ping-pong attributes to perform a data in transaction using a non ping-pong endpoint: 1. the microcontroller checks if it is possible to write in the fifo by polling t xpktrdy in the endpoint?s usb_csrx register (txpktrdy must be cleared). 2. the microcontroller writes data to be sent in the endpoint?s fifo, writing zero or more byte values in the endpoint?s usb_fdrx register, 3. the microcontroller notifies the usb peripheral it has finished by setting the txpk- trdy in the endpoint?s usb_csrx register. 4. the microcontroller is notified that the endpoint?s fifo has been released by the usb device when txcomp in the endpoint?s usb_csrx register has been set. then an interrupt for the corresponding endpoint is pending while txcomp is set. txcomp is set by the usb device when it has received an ack pid signal for the data in packet. an interrupt is pending while txcomp is set. note: refer to chapter 8 of the universal serial bus specification, rev 2.0, for more information on the data in protocol layer. rx_data_bko (usb_csrx) ack pid data out data out pid nak pid ack pid data setup setup pid usb bus packets rxsetup flag set by usb device cleared by firmware set by usb device peripheral fifo (dpr) content data setup data xx xx out interrupt pending setup received setup handled by firmware data out received data out data out pid
401 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 173. data in transfer for non ping-pong endpoint using endpoints with ping-pong attribute the use of an endpoint with ping-pong attributes is necessary during isochronous transfer. to be able to guarantee a constant bandwidth, the microcontroller must prepare the next data payload to be sent while the current one is being sent by the usb device. thus two banks of memory are used. while one is available for the microcontroller, the other one is locked by the usb device. figure 174. bank swapping data in transfer for ping-pong endpoints when using a ping-pong endpoint, the following procedures are required to perform data in transactions: 1. the microcontroller checks if it is possible to write in the fifo by po lling t xpktrdy to be cleared in the endpoint?s usb_csrx register. 2. the microcontroller writes the first data payload to be sent in the fifo (bank 0), writing zero or more byte values in the endpoint?s usb_fdrx register. usb bus packets data in 2 data in nak ack data in 1 fifo (dpr) content load in data in 2 load in progress data in 1 cleared by firmware start to write data payload in fifo set by the firmware data payload written in fifo txcomp flag (usb_csrx) txpktrdy flag (usb_csrx) cleared by usb device pid data in data in pid pid pid pid ack pid progress prevous data in tx microcontroller load data in fifo data is sent on usb bus interrupt pending interrupt pending usb device usb bus read write read and write at the same time 1 st data payload 2 nd data payload 3 rd data payload 3 rd data payload 2 nd data payload 1 st data payload data in packet data in packet data in packet microcontroller endpoint 1 bank 0 endpoint 1 bank 1 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 1
402 at91sam7s64 preliminary 6070a?atarm?28-oct-04 3. the microcontroller notifies the usb peripheral it has finished writing in bank 0 of the fifo by setting the txpktrdy in the endpoint?s usb_csrx register. 4. without waiting for txpktrdy to be cleared, the microcontroller writes the second data payload to be sent in the fifo (bank 1), writing zero or more byte values in the endpoint?s usb_fdrx register. 5. the microcontroller is notified that the first bank has been released by the usb device when txcomp in the endpoint?s usb_csrx register is set. an interrupt is pending while txcomp is being set. 6. once the microcontroller has received txcomp for the first bank, it notifies the usb device that it has prepared the second bank to be sent rising txpktrdy in the end- point?s usb_csrx register. 7. at this step, bank 0 is available and the microcontroller can prepare a third data pay- load to be sent . figure 175. data in transfer for ping-pong endpoint warning: there is software critical path due to the fact that once the second bank is filled, the driver has to wait for tx_comp to set tx_pktrdy. if the delay between receiving tx_comp is set and tx_pktrdy is set is too long, some data in packets may be nacked, reducing the bandwidth. data out transaction data out transactions are used in control, isochronous, bulk and interrupt transfers and con- duct the transfer of data from the host to the device. data out transactions in isochronous transfers must be done using endpoints with ping-pong attributes. data out transaction without ping-pong attributes to perform a data out transaction, using a non ping-pong endpoint: 1. the host generates a data out packet. 2. this packet is received by the usb device endpoint. while the fifo associated to this endpoint is being used by the microcontroller, a nak pid is returned to the host. once data in data in read by usb device read by usb device bank 1 bank 0 fifo (dpr) txcomp flag (usb_csrx) interrupt cleared by firmware set by usb device txpktrdy flag (usb_mcsrx) ack pid data in pid ack pid set by firmware, data payload written in fifo bank 1 cleared by usb device, data payload fully transmitted data in pid usb bus packets set by usb device set by firmware, data payload written in fifo bank 0 written by fifo (dpr) microcontroller written by microcontroller written by microcontroller microcontroller load data in bank 0 microcontroller load data in bank 1 usb device send bank 0 microcontroller load data in bank 0 usb device send bank 1 interrupt pending
403 at91sam7s64 preliminary 6070a?atarm?28-oct-04 the fifo is available, data are written to the fifo by the usb device and an ack is automatically carried out to the host. 3. the microcontroller is notified that the usb device has received a data payload polling rx_data_bk0 in the endpoint?s usb_csrx register. an interrupt is pending for this endpoint while rx_data_bk0 is set. 4. the number of bytes available in the fifo is made available by reading r xbytecnt in the endpoint?s usb_csrx register. 5. the microcontroller carries out data received from the endpoint?s memory to its mem- ory. data received is available by reading the endpoint?s usb_fdrx register. 6. the microcontroller notifies the usb device that it has finished the transfer by clearing rx_data_bk0 in the endpoint?s usb_csrx register. 7. a new data out packet can be accepted by the usb device. figure 176. data out transfer for non ping-pong endpoints an interrupt is pending while the flag rx_data_bk0 is set. memory transfer between the usb device, the fifo and microcontroller memory can not be done after rx_data_bk0 has been cleared. otherwise, the usb device would accept the next data out transfer and over- write the current data out packet in the fifo. using endpoints with ping-pong attributes during isochronous transfer, using an endpoint with ping-pong attributes is obligatory. to be able to guarantee a constant bandwidth, the microcontroller must read the previous data pay- load sent by the host, while the current data payload is received by the usb device. thus two banks of memory are used. while one is available for the microcontroller, the other one is locked by the usb device. ack pid data out nak pid pid pid pid pid data out2 ack data out data out 1 usb bus packets rx_data_bk0 set by usb device cleared by firmware, data payload written in fifo fifo (dpr) content written by usb device microcontroller read data out 1 data out 1 data out 2 host resends the next data payload microcontroller transfers data host sends data payload data out2 data out2 host sends the next data payload written by usb device (usb_csrx) interrupt pending
404 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 177. bank swapping in data out transfers for ping-pong endpoints when using a ping-pong endpoint, the following procedures are required to perform data out transactions: 1. the host generates a data out packet. 2. this packet is received by the usb device endpoint. it is written in the endpoint?s fifo bank 0. 3. the usb device sends an ack pid packet to the host. the host can immediately send a second data out packet. it is accepted by the device and copied to fifo bank 1. 4. the microcontroller is notified that the usb device has received a data payload, polling rx_data_bk0 in the endpoint?s usb_csrx register. an interrupt is pending for this endpoint while rx_data_bk0 is set. 5. the number of bytes available in the fifo is made available by reading r xbytecnt in the endpoint?s usb_csrx register. 6. the microcontroller transfers out data received from the endpoint?s memory to the microcontroller?s memory. data received is made available by reading the endpoint?s usb_fdrx register. 7. the microcontroller notifies the usb peripheral device that it has finished the transfer by clearing rx_data_bk0 in the endpoint?s usb_csrx register. 8. a third data out packet can be accepted by the usb peripheral device and copied in the fifo bank 0. 9. if a second data out packet has been received, the microcontroller is notified by the flag rx_data_bk1 set in the endpoint?s usb_csrx register. an interrupt is pending for this endpoint while rx_data_bk1 is set. 10. the microcontroller transfers out data received from the endpoint?s memory to the microcontroller?s memory. data received is available by reading the endpoint?s usb_fdrx register. 11. the microcontroller notifies the usb device it has finished the transfer by clearing rx_data_bk1 in the endpoint?s usb_csrx register. 12. a fourth data out packet can be accepted by the usb device and copied in the fifo bank 0. usb device usb bus read write write and read at the same time 1 st data payload 2 nd data payload 3 rd data payload 3 rd data payload 2 nd data payload 1 st data payload data in packet data in packet data in packet microcontroller endpoint 1 bank 0 endpoint 1 bank 1 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 1
405 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 178. data out transfer for ping-pong endpoint note: an interrupt is pending while the rx_data_bk0 or rx_data_bk1 flag is set. warning : when rx_data_bk0 and rx_data_bk1 are both set, there is no way to deter- mine which one to clear first. thus the software must keep an internal counter to be sure to clear alternatively rx_data_bk0 then rx_data_bk1. this situation may occur when the software application is busy elsewhere and the two banks are filled by the usb host. once the application comes back to the usb driver, the two flags are set. status transaction a status transaction is a special type of host-to-device transaction used only in a control trans- fer. the control transfer must be performed using endpoints with no ping-pong attributes. according to the control sequence (read or write), the usb device sends or receives a status transaction. a p data out pid ack data out 3 data out data out 2 data out data out 1 pid data out 3 data out 1 data out1 data out 2 data out 2 pid pid pid ack cleared by firmware usb bus packets rx_data_bk0 flag rx_data_bk1 flag set by usb device, data payload written in fifo endpoint bank 1 fifo (dpr) bank 0 bank 1 write by usb device write in progress read by microcontroller read by microcontroller set by usb device, data payload written in fifo endpoint bank 0 host sends first data payload microcontroller reads data 1 in bank 0, host sends second data payload microcontroller reads data2 in bank 1, host sends third data payload cleared by firmware write by usb device fifo (dpr) (usb_csrx) (usb_csrx) interrupt pending interrupt pending
406 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 179. control read and write sequences notes: 1. during the status in stage, the host waits for a zero length packet (data in transaction with no data) from the device using data1 pid. refer to chapter 8 of the universal serial bus specification, rev. 2.0, for more information on the protocol layer. 2. during the status out stage, the host emits a zero length packet to the device (data out transaction with no data). status in transfer once a control request has been processed, the device returns a status to the host. this is a zero length data in transaction. 1. the microcontroller waits for txpktrdy in the usb_csrx endpoint?s register to be cleared. (at this step, txpktrdy must be cleared because the previous transaction was a setup transaction or a data out transaction.) 2. without writing anything to the usb_fdrx endpoint?s register, the microcontroller sets txpktrdy. the usb device generates a data in packet using data1 pid. 3. this packet is acknowledged by the host and txpktrdy is set in the usb_csrx end- point?s register. figure 180. data out followed by status in transfer. control read setup tx data out tx data out tx data stage control write setup stage setup stage setup tx setup tx no data control data in tx data in tx status stage status stage status in tx status out tx status in tx data stage setup stage status stage data in nak data out data out ack pid pid pid pid usb bus packets rx_data_bko (usb_csrx) cleared by firmware set by usb device cleared by usb device txpktrdy (usb_csrx) set b y firmware host sends the last data payload to the device device sends a status in to the host interrupt pending
407 at91sam7s64 preliminary 6070a?atarm?28-oct-04 status out transfer once a control request has been processed and the requested data returned, the host acknowledges by sending a zero length packet. this is a zero length data out transaction. 1. the usb device receives a zero length packet. it sets rx_data_bk0 flag in the usb_csrx register and acknowledges the zero length packet. 2. the microcontroller is notified that the usb device has received a zero length packet sent by the host polling rx_data_bk0 in the usb_csrx register. an interrupt is pending while rx_data_bk0 is set. the number of bytes received in the endpoint?s usb_bcr register is equal to zero. 3. the microcontroller must clear rx_data_bk0. figure 181. data in followed by status out transfer stall handshake a stall handshake can be used in one of two distinct occasions. (for more information on the stall handshake, refer to chapter 8 of the universal serial bus specification, rev 2.0. ) a functional stall is used when the halt feature associated with the endpoint is set. (refer to chapter 9 of the universal serial bus specification, rev 2.0, for more information on the halt feature.) to abort the current request, a protocol stall is used, but uniquely with control transfer. the following procedure generates a stall packet: 1. the microcontroller sets the forcestall flag in the usb_csrx endpoint?s register. 2. the host receives the stall packet. 3. the microcontroller is notified that the device has sent the stall by polling the stallsent to be set. an endpoint interrupt is pending while stallsent is set. the microcontroller must clear stallsent to clear the interrupt. when a setup transaction is received after a stall handshake, stallsent must be cleared in order to prevent interrupts due to stallsent being set. data out data in data in ack pid pid pid ack pid rx_data_bko (usb_csrx) txcomp (usb_csrx) set by usb device usb bus packets cleared by firmware cleared by firmware set by usb device device sends a status out to host device sends the last data payload to host interrupt pending
408 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 182. stall handshake (data in transfer) figure 183. stall handshake (data out transfer) data in stall pid pid usb bus packets cleared by firmware set by firmware forcestall stallsent set by usb device cleared by firmware interrupt pending data out pid stall pid data out usb bus packets cleared by firmware set by firmware forcestall stallsent set by usb device interrupt pending
409 at91sam7s64 preliminary 6070a?atarm?28-oct-04 controlling device states a usb device has several possible states. refer to chapter 9 of the universal serial bus specification, rev 2.0 . figure 184. usb device state diagram movement from one state to another depends on the usb bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). after a period of bus inactivity, the udp device enters suspend mode. accepting sus- pend/resume requests from the usb host is mandatory. constraints in suspend mode are very strict for bus-powered applications; devices may not consume more than 500 a on the usb bus. while in suspend mode, the host may wake up a device by sending a resume signal (bus activity) or a usb device may send a wake-up request to the host, e.g., waking up a pc by moving a usb mouse. the wake-up feature is not mandatory for all devices and must be negotiated with the host. attached suspended suspended suspended suspended hub reset or deconfigured hub configured bus inactive bus activity bus inactive bus activity bus inactive bus activity bus inactive bus activity reset reset address assigned device deconfigured device configured powered default address configured power interruption
410 at91sam7s64 preliminary 6070a?atarm?28-oct-04 from powered state to default state after its connection to a usb host, the usb device waits for an end-of-bus reset. the usb host stops driving a reset state once it has detected the device?s pull-up on dp. the unmasked flag endburst is set in the register udp_isr and an interrupt is triggered. the udp soft- ware enables the default endpoint, setting the epeds flag in the udp_csr[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 to the udp_ier register. the enu- meration then begins by a control transfer. from default state to address state after a set address standard device request, the usb host peripheral enters the address state. before this, it achieves the status in transaction of the control transfer, i.e., the udp device sets its new address once the txcomp flag in the udp_csr[0] register has been received and cleared. to move to address state, the driver software sets the fadden flag in the udp_glb_state, sets its new address, and sets the fen bit in the udp_faddr register. from address state to configured state once a valid set configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. this is done by setting the epeds and eptype fields in the udp_csrx registers and, optionally, enabling corre- sponding interrupts in the udp_ier register. enabling suspend when a suspend (no bus activity on the usb bus) is detected, the rxsusp signal in the udp_isr register is set. this triggers an interrupt if the corresponding bit is set in the udp_imr register. this flag is cleared by writing to the udp_icr register. then the device enters suspend mode. as an example, the microcontroller switches to slow clock, disables the pll and main oscillator, and goes into idle mode. it ma y also switch off other devices on the board. the usb device peripheral clocks may be switched off. however, the transceiver and the usb peripheral must not be switched off, otherwise the resume is not detected. receiving a host resume in suspend mode, the usb transceiver and the usb peripheral must be powered to detect the resume. however, the usb device peripheral may not be clocked as the wakeup signal is asynchronous. once the resume is detected on the bus, the signal wakeup in the udp_isr is set. it may generate an interrupt if the corresponding bit in the udp_imr register is set. this interrupt may be used to wake-up the core, enable pll and main oscillators and configure clocks. the wakeup bit must be cleared as soon as possible by setting wakeup in the udp_icr register. sending an external resume the external resume is negotiated with the host and enabled by setting the esr bit in the usb_glb_state. an asynchronous event on the ext_resume_pin of the peripheral gener- ates a wakeup interrupt. on early versions of the usp peripheral, the k-state on the usb line is generated immediately. this means that the usb device must be able to answer to the host very quickly. on recent versions, the software sets the rmwupe bit in the udp_glb_state register once it is ready to communicate with the host. the k-state on the bus is then generated. the wakeup bit must be cleared as soon as possible by setting wakeup in the udp_icr register.
411 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usb device port (udp) user interface notes: 1. the addresses of the usb_csrx registers are calculated as: 0x030 + 4(endpoint number - 1). 2. the addresses of the usb_fdrx registers are calculated as: 0x050 + 4(endpoint number - 1). table 83. usb device port (udp) register mapping offset register name access reset state 0x000 frame number register usb_frm_num read 0x0000_0000 0x004 global state register usb_glb_stat read/write 0x0000_0010 0x008 function address register usb_faddr read/write 0x0000_0100 0x00c reserved ? ? ? 0x010 interrupt enable register usb_ier write 0x014 interrupt disable register usb_idr write 0x018 interrupt mask register usb_imr read 0x0000_1200 0x01c interrupt status register usb_isr read 0x0000_0000 0x020 interrupt clear register usb_icr write 0x024 reserved ? ? ? 0x028 reset endpoint register usb_rst_ep read/write 0x02c reserved ? ? ? 0x030 endpoint 0 control and status register usb _csr0 read/write 0x0000_0000 . . . . . . see note 1 endpoint 3 control and status register usb _csr3 read/write 0x0000_0000 0x050 endpoint 0 fifo data register usb_fdr0 read/write 0x0000_0000 . . . . . . see note 2 endpoint 3 fifo data register usb_fdr3 read/write 0x0000_0000 0x070 reserved ? ? ? 0x074 transceiver control register usb_txvc read/write 0x0000_0100 0x078 - 0x0fc reserved ? ? ?
412 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usb frame number register register name: usb_frm_num access type: read-only frm_num[10:0]: frame number as defined in the packet field formats this 11-bit value is incremented by the host on a per frame basis. this value is updated at each start of frame. value updated at the sof_eop (start of frame end of packet). frm_err: frame error this bit is set at sof_eop when the sof packet is received containing an error. this bit is reset upon receipt of sof_pid. frm_ok: frame ok this bit is set at sof_eop when the sof packet is received without any error. this bit is reset upon receipt of sof_pid (packet identification). in the interrupt status register, the sof interrupt is updated upon receiving sof_pid. this bit is set without waiting for eop. note: in the 8-bit register interface, frm_ok is bit 4 of frm_num_h and frm_err is bit 3 of frm_num_l. 31 30 29 28 27 26 25 24 --- --- --- --- --- --- --- --- 23 22 21 20 19 18 17 16 ??????frm_okfrm_err 15 14 13 12 11 10 9 8 ????? frm_num 76543210 frm_num
413 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usb global state register register name: usb_glb_stat access type: read/write this register is used to get and set the device state as specified in chapter 9 of the usb serial bus specification, rev.2.0 . fadden: function address enable read: 0 = device is not in address state. 1 = device is in address state. write: 0 = no effect, only a reset can bring back a device to the default state. 1 = sets device in address state. this occurs after a successful set address request. beforehand, the usb_faddr regis- ter must have been initialized with set address parameters. set address must complete the status stage before setting fadden. refer to chapter 9 of the universal serial bus specification, rev. 2.0 for more details. confg: configured read: 0 = device is not in configured state. 1 = device is in configured state. write: 0 = sets device in a non configured state 1 = sets device in configured state. the device is set in configured state when it is in address st ate and receives a successful set configuration request. refer to chapter 9 of the universal serial bus specification, rev. 2.0 for more details. esr: enable send resume 0 = disables the remote wake up sequence. 1 = remote wake up can be processed and the pin send_resume is enabled. rsminpr: a resume has been sent to the host read: 0 = no effect. 1 = a resume has been received from the host during remote wake up feature. rmwupe: remote wake up enable 0 = must be cleared after receiving any host packet or sof interrupt. 1 = enables the k-state on the usb cable if esr is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?? 76543210 ? ? ? rmwupe rsminpr esr confg fadden
414 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usb function address register register name: usb_faddr access type: read/write fadd[6:0]: function address value the function address value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. refer to the universal serial bus specification, rev. 2.0 for more information. after power up or reset, the function address value is set to 0. fen: function enable read: 0 = function endpoint disabled. 1 = function endpoint enabled. write: 0 = disables function endpoint. 1 = default value. the function enable bit (fen) allows the microcontroller to enable or disable the function endpoints. the microcontroller sets this bit after receipt of a reset from the host. once this bit is set, the usb device is able to accept and transfer data packets from and to the host. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?fen 76543210 ?fadd
415 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usb interrupt enable register register name: usb_ier access type: write-only ep0int: enable endpoint 0 interrupt ep1int: enable endpoint 1 interrupt ep2int: enable endpoint 2interrupt ep3int: enable endpoint 3 interrupt 0 = no effect. 1 = enables corresponding endpoint interrupt. rxsusp: enable usb suspend interrupt 0 = no effect. 1 = enables usb suspend interrupt. rxrsm: enable usb resume interrupt 0 = no effect. 1 = enables usb resume interrupt. extrsm: enable external resume interrupt 0 = no effect. 1 = enables external resume interrupt. sofint: enable start of frame interrupt 0 = no effect. 1 = enables start of frame interrupt. wakeup: enable usb bus wakeup interrupt 0 = no effect. 1 = enables usb bus interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup ? sofint extrsm rxrsm rxsusp 76543210 ? ? ep3int ep2int ep1int ep0int
416 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usb interrupt disable register register name: usb_idr access type: write-only ep0int: disable endpoint 0 interrupt ep1int: disable endpoint 1 interrupt ep2int: disable endpoint 2 interrupt ep3int: disable endpoint 3 interrupt 0 = no effect. 1 = disables corresponding endpoint interrupt. rxsusp: disable usb suspend interrupt 0 = no effect. 1 = disables usb suspend interrupt. rxrsm: disable usb resume interrupt 0 = no effect. 1 = disables usb resume interrupt. extrsm: disable external resume interrupt 0 = no effect. 1 = disables external resume interrupt. sofint: disable start of frame interrupt 0 = no effect. 1 = disables start of frame interrupt wakeup: disable usb bus interrupt 0 = no effect. 1 = disables usb bus wakeup interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup ? sofint extrsm rxrsm rxsusp 76543210 ? ? ep3int ep2int ep1int ep0int
417 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usb interrupt mask register register name: usb_imr access type: read-only ep0int: mask endpoint 0 interrupt ep1int: mask endpoint 1 interrupt ep2int: mask endpoint 2 interrupt ep3int: mask endpoint 3 interrupt 0 = corresponding endpoint interrupt is disabled. 1 = corresponding endpoint interrupt is enabled. rxsusp: mask usb suspend interrupt 0 = usb suspend interrupt is disabled. 1 = usb suspend interrupt is enabled. rxrsm: mask usb resume interrupt. 0 = usb resume interrupt is disabled. 1 = usb resume interrupt is enabled. extrsm: mask external resume interrupt 0 = external resume interrupt is disabled. 1 = external resume interrupt is enabled. sofint: mask start of frame interrupt 0 = start of frame interrupt is disabled. 1 = start of frame interrupt is enabled. wakeup: usb bus wakeup interrupt 0 = usb bus wakeup interrupt is disabled. 1 = usb bus wakeup interrupt is enabled. note: when the usb block is in suspend mode, the application may power down the usb logic. in this case, any usb host resume request that is made must be taken into account and, thus, the reset value of the rxrsm bit of the register usb_imr is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup ? sofint extrsm rxrsm rxsusp 76543210 ? ? ep3int ep2int ep1int ep0int
418 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usb interrupt status register register name: usb_isr access type: read-only ep0int: endpoint 0 interrupt status 0 = no endpoint0 interrupt pending. 1 = endpoint0 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading usb_csr0: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep0int is a sticky bit. interrupt remains valid until ep0int is cleared by writing in the corresponding usb_csr0 bit. ep1int: endpoint 1 interrupt status 0 = no endpoint1 interrupt pending. 1 = endpoint1 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading usb_csr1: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep1int is a sticky bit. interrupt remains valid until ep1int is cleared by writing in the corresponding usb_csr1 bit. ep2int: endpoint 2 interrupt status 0 = no endpoint2 interrupt pending. 1 = endpoint2 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading usb_csr2: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup endbusres sofint extrsm rxrsm rxsusp 76543210 ? ? ep3int ep2int ep1int ep0int
419 at91sam7s64 preliminary 6070a?atarm?28-oct-04 ep2int is a sticky bit. interrupt remains valid until ep2int is cleared by writing in the corresponding usb_csr2 bit. ep3int: endpoint 3 interrupt status 0 = no endpoint3 interrupt pending. 1 = endpoint3 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading usb_csr3: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep3int is a sticky bit. interrupt remains valid until ep3int is cleared by writing in the corresponding usb_csr3 bit. rxsusp: usb suspend interrupt status 0 = no usb suspend interrupt pending. 1 = usb suspend interrupt has been raised. the usb device sets this bit when it detects no activity for 3ms. the usb device enters suspend mode. rxrsm: usb resume interrupt status 0 = no usb resume interrupt pending. 1 =usb resume interrupt has been raised. the usb device sets this bit when a usb resume signal is detected at its port. extrsm: external resume interrupt status 0 = no external resume interrupt pending. 1 = external resume interrupt has been raised. this interrupt is raised when, in suspend mode, an asynchronous rising edge on the send_resume is detected. if rmwupe = 1, a resume state is sent in the usb bus. sofint: start of frame interrupt status 0 = no start of frame interrupt pending. 1 = start of frame interrupt has been raised. this interrupt is raised each time a sof token has been detected. it can be used as a synchronization signal by using isochronous endpoints. endbusres: end of bus reset interrupt status 0 = no end of bus reset interrupt pending. 1 = end of bus reset interrupt has been raised. this interrupt is raised at the end of a usb reset sequence . the usb device must prepare to receive requests on the end- point 0. the host starts the enumeration, then performs the configuration. wakeup: usb resume interrupt status 0 = no wakeup interrupt pending. 1 = a wakeup interrupt (usb host sent a resume or reset) occurred since the last clear.
420 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usb interrupt clear register register name: usb_icr access type: write-only rxsusp: clear usb suspend interrupt 0 = no effect. 1 = clears usb suspend interrupt. rxrsm: clear usb resume interrupt 0 = no effect. 1 = clears usb resume interrupt. extrsm: clear external resume interrupt 0 = no effect. 1 = clears external resume interrupt. sofint: clear start of frame interrupt 0 = no effect. 1 = clears start of frame interrupt. endburst: clear end of bus reset interrupt 0 = no effect. 1 = clears start of frame interrupt. wakeup: clear wakeup interrupt 0 = no effect. 1 = clears wakeup interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup endburst sofint extrsm rxrsm rxsusp 76543210 ????????
421 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usb reset endpoint register register name: usb_rst_ep access type: read/write ep0: reset endpoint 0 ep1: reset endpoint 1 ep2: reset endpoint 2 ep3: reset endpoint 3 this flag is used to reset the fifo associated with the endpoint and the bit rxbytecount in the register udp_csrx.it also resets the data toggle to data0. it is useful after removing a halt condition on a bulk endpoint. refer to chapter 5.8.5 in the usb serial bus specification, rev.2.0 . warning: this flag must be cleared at the end of the reset. it does not clear usb_csrx flags. 0 = no reset. 1 = forces the corresponding endpoint fif0 pointers to 0, therefore rxbytecnt field is read at 0 in usb_csrx register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?? 76543210 ? ? ep3 ep2 ep1 ep0
422 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usb endpoint control and status register register name: usb_csrx [x = 0..3] access type: read/write txcomp: generates an in packet with data previously written in the dpr this flag generates an interrupt while it is set to one. write (cleared by the firmware): 0 = clear the flag, clear the interrupt. 1 = no effect. read (set by the usb peripheral): 0 = data in transaction has not been acknowledged by the host. 1 = data in transaction is achieved, acknowledged by the host. after having issued a data in transaction setting txpktrdy, the device firmware waits for txcomp to be sure that the host has acknowledged the transaction. rx_data_bk0: receive data bank 0 this flag generates an interrupt while it is set to one. write (cleared by the firmware): 0 = notify usb peripheral device that data have been read in the fifo's bank 0. 1 = no effect. read (set by the usb peripheral): 0 = no data packet has been received in the fifo's bank 0 1 = a data packet has been received, it has been stored in the fifo's bank 0. when the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the fifo to the microcontroller memory. the number of bytes received is available in rxbytcent field. bank 0 fifo values are read through the usb_fdrx register. once a transfer is done, the device firmware must release bank 0 to the usb peripheral device by clearing rx_data_bk0. rxsetup: sends stall to the host (control endpoints) this flag generates an interrupt while it is set to one. read: 0 = no setup packet available. 1 = a setup data packet has been sent by the host and is available in the fifo. write: 0 = device firmware notifies the usb peripheral device that it has read the setup data in the fifo. 31 30 29 28 27 26 25 24 ????? r xbytecnt 23 22 21 20 19 18 17 16 rxbytecnt 15 14 13 12 11 10 9 8 epeds ? ? ? dtgle eptype 76543210 dir rx_data_ bk1 force stall txpktrdy stallsent isoerror rxsetup rx_data_ bk0 txcomp
423 at91sam7s64 preliminary 6070a?atarm?28-oct-04 1 = no effect. this flag is used to notify the usb device firmware that a valid setup data packet has been sent by the host and success- fully received by the usb device. the usb device firmware may transfer setup data from the fifo by reading the usb_fdrx register to the microcontroller memory. once a transfer has been done, rxsetup must be cleared by the device firmware. ensuing data out transactions is not accepted while rxsetup is set. stallsent: stall sent (control, bulk interrupt endpoints) / isoerror (isochronous endpoints) this flag generates an interrupt while it is set to one. stallsent: this ends a stall handshake. read: 0 = the host has not acknowledged a stall. 1 = host has acknowledged the stall. write: 0 = resets the stallsent flag, clears the interrupt. 1 = no effect. this is mandatory for the device firmware to clear this flag. otherwise the interrupt remains. refer to chapters 8.4.5 and 9.4.5 of the universal serial bus specification, rev. 2.0 for more information on the stall handshake. isoerror: a crc error has been detected in an isochronous transfer. read: 0 = no error in the previous isochronous transfer. 1 = crc error has been detected, data available in the fifo are corrupted. write: 0 = resets the isoerror flag, clears the interrupt. 1 = no effect. txpktrdy: transmit packet ready this flag is cleared by the usb device. this flag is set by the usb device firmware. read: 0 = data values can be written in the fifo. 1 = data values can not be written in the fifo. write: 0 = no effect. 1 = a new data payload is has been written in the fifo by the firmware and is ready to be sent. this flag is used to generate a data in transaction (device to host). device firmware checks that it can write a data payload in the fifo, checking that txpktrdy is cleared. transfer to the fifo is d one by writing in the usb_fdrx register. once the data payload has been transferred to the fifo, the firmware notifies the usb device setting txpktrdy to one. usb bus transactions can start. txcomp is set once the data payload has been received by the host. forcestall: force stall (used by control, bulk and isochronous endpoints) write-only 0 = no effect. 1 = sends stall to the host. refer to chapters 8.4.5 and 9.4.5 of the universal serial bus specification, rev. 2.0 for more information on the stall handshake.
424 at91sam7s64 preliminary 6070a?atarm?28-oct-04 control endpoints: during the data stage and status stage, this indicates that the microcontroller cannot complete the request. bulk and interrupt endpoints: notifies the host that the endpoint is halted. the host acknowledges the stall, device firmware is notified by the stallsent flag. rx_data_bk1: receive data bank 1 (only used by endpoints with ping-pong attributes) this flag generates an interrupt while it is set to one. write (cleared by the firmware): 0 = notifies usb device that data have been read in the fifo?s bank 1. 1 = no effect. read (set by the usb peripheral): 0 = no data packet has been received in the fifo's bank 1. 1 = a data packet has been received, it has been stored in fifo's bank 1. when the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the fifo to microcontroller memory. the number of bytes received is available in rxbytecnt field. bank 1 fifo values are read through usb_fdrx register. once a transfer is done, the device firmware must release bank 1 to the usb device by clear- ing rx_data_bk1. dir: transfer direction (only available for control endpoints) read/write 0 = allows data out transactions in the control data stage. 1 = enables data in transactions in the control data stage. refer to chapter 8.5.3 of the universal serial bus specification, rev. 2.0 for more information on the control data stage. this bit must be set before usb_csrx/rxsetup is cleared at the end of the setup stage. according to the request sent in the setup data packet, the data stage is either a device to host (dir = 1) or host to device (dir = 0) data transfer. it is not necessary to check this bit to reverse direction for the status stage. eptype[2:0]: endpoint type dtgle: data toggle read-only 0 = identifies data0 packet. 1 = identifies data1 packet. refer to chapter 8 of the universal serial bus specification, rev. 2.0 for more information on data0, data1 packet definitions. read/write 000 control 001 isochronous out 101 isochronous in 010 bulk out 110 bulk in 011 interrupt out 111 interrupt in
425 at91sam7s64 preliminary 6070a?atarm?28-oct-04 epeds: endpoint enable disable read: 0 = endpoint disabled. 1 = endpoint enabled. write: 0 = disables endpoint. 1 = enables endpoint. rxbytecnt[10:0]: number of bytes available in the fifo read-only when the host sends a data packet to the device, the usb device stores the data in the fifo and notifies the microcontrol- ler. the microcontroller can load the data from the fifo by reading r xbytecent bytes in the usb_fdrx register. usb fifo data register register name: usb_fdrx [x = 0..3] access type: read/write fifo_data[7:0]: fifo data value the microcontroller can push or pop values in the fifo through this register. rxbytecnt in the corresponding usb_csrx register is the number of bytes to be read from the fifo (sent by the host). the maximum number of bytes to write is fixed by the max packet size in the standard endpoint descriptor. it can not be more than the physical memory size associated to the endpoint. refer to the universal serial bus specification, rev. 2.0 for more information. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?? 76543210 fifo_data
426 at91sam7s64 preliminary 6070a?atarm?28-oct-04 usb transceiver control register register name: usb_txvc access type: read/write txvdis: transceiver disable when udp is disabled, power consumption can be reduced significantly by disabling the embedded transceiver. this can be done by setting txvdis field. to enable the transceiver, txvdis must be cleared. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ? txvdis 76543210 ?????? ??
427 at91sam7s64 preliminary 6070a?atarm?28-oct-04 analog-to-digital converter (adc) overview the adc is based on a successive approximation register (sar) 10-bit analog-to-digital converter (adc). it also integrates an 8-to-1 analog multiplexer, making possible the analog- to-digital conversions of up to eight analog lines. the conversions extend from 0v to advref. the adc supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for all channels, as well as in a channel-dedicated register. software trigger, external trigger on rising edge of the adtrg pin or internal triggers from timer counter out- put(s) are configurable. the adc also integrates a sleep mode and a conversion sequencer and connects with a pdc channel. these features reduce both power consumption and processor intervention. finally, the user can configure adc timings, such as startup time and sample & hold time. block diagram figure 185. analog-to-digital converter block diagram adc interrupt adc adtrg ad0 vddin advref gnd ad1 ad2 ad3 trigger selection control logic successive approximation register analog-to-digital converter timer counter channels user interface aic peripheral bridge apb pdc asb ad4 ad5 ad6 ad7 pio
428 at91sam7s64 preliminary 6070a?atarm?28-oct-04 signal description product dependencies power management the adc is automatically clocked after the first conversion in normal mode. in sleep mode, the adc clock is automatically stopped after each conversion. as the logic is small and the adc cell can be put into sleep mode, the power management controller has no effect on the adc behavior. interrupt sources the adc interrupt line is connected on one of the internal sources of the advanced interrupt controller. using the adc interrupt requires the aic to be programmed first. analog inputs the pins ad0 to ad7 can be multiplexed with pio lines. in this case, the assignment of the adc input is automatically done as soon as the corresponding channel is enabled by writing the register adc_cher. by default, after reset, the pio line is configured as input with its pull- up enabled and the adc input is connected to the gnd. i/o lines the pin adtrg may be shared with other peripheral functions through the pio controller. in this case, the pio controller should be set accordingly to assign the pin adtrg to the adc function. timer triggers timer counters may or may not be used as hardware triggers depending on user require- ments. thus, some or all of the timer counters may be non-connected. conversion performances for performance and electrical characteristics of the adc, see ?adc characteristics? on page 453. table 84. adc pin description pin name description vddin analog power supply advref reference voltage ad0 - ad7 analog input channels adtrg external trigger
429 at91sam7s64 preliminary 6070a?atarm?28-oct-04 functional description analog-to-digital conversion the adc uses the adc clock to perform conversions. converting a single analog value to a 10-bit digital data requires sample and hold clock cycles as defined in the field shtim of the ?adc mode register? on page 435 and 10 adc clock cycles. the adc clock frequency is selected in the prescal field of the mode register (adc_mr). the adc clock range is between mck/2, if prescal is 0, and mck/128, if prescal is set to 63 (0x3f). prescal must be programmed in order to provide an adc clock frequency according to the parameters given in the product definition section. conversion reference the conversion is performed on a full range between 0v and the reference voltage pin advref. analog inputs between these voltages convert to values based on a linear conversion. conversion resolution the adc supports 8-bit or 10-bit resolutions. the 8-bit selection is performed by setting the bit lowres in the adc mode register (adc_mr). by default, after a reset, the resolution is the highest and the data field in the data registers is fully used. by setting the bit lowres, the adc switches in the lowest resolution and the conversion results can be read in the eight low- est significant bits of the data registers. the two highest bits of the data field in the corresponding adc_cdr register and of the ldata field in the adc_lcdr register read 0. moreover, when a pdc channel is connected to the adc, 10-bit resolution sets the transfer request sizes to 16-bit. setting the bit lowres automatically switches to 8-bit data transfers. in this case, the destination buffers are optimized. conversion results when a conversion is completed, the resulting 10-bit digital value is stored in the channel data register (adc_cdr) of the current channel and in the adc last converted data regis- ter (adc_lcdr). the channel eoc bit in the status register (adc_sr) is set and the drdy is set. in the case of a connected pdc channel, drdy rising triggers a data transfer request. in any case, either eoc and drdy can trigger an interrupt. reading one of the adc_cdr registers clears the corresponding eoc bit. reading adc_lcdr clears the drdy bit and the eoc bit co rresponding to the last converted channel.
430 at91sam7s64 preliminary 6070a?atarm?28-oct-04 figure 186. eocx and drdy flag behavior conversion time read the adc_cdrx eocx drdy read the adc_lcdr chx (adc_chsr) (adc_sr) (adc_sr) write the adc_cr with start = 1 conversion time write the adc_cr with start = 1
431 at91sam7s64 preliminary 6070a?atarm?28-oct-04 if the adc_cdr is not read before further incoming data is converted, the corresponding overrun error (ovre) flag is set in the status register (adc_sr). in the same way, new data converted when drdy is high sets the bit govre (general over- run error) in adc_sr. the ovre and govre flags are automatically cleared when adc_sr is read. figure 187. govre and ovrex flag behavior warning: if the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associated data and its corresponding eoc and ovre flags in adc_sr are unpredictable. conversion triggers conversions of the active analog channels are started with a software or a hardware trigger. the software trigger is provided by writing the control register (adc_cr) with the bit start at 1. the hardware trigger can be one of the tioa outputs of the timer counter channels, or the external trigger input of the adc (adtrg). the hardware trigger is selected with the field trgsel in the mode register (adc_mr). the selected hardware trigger is enabled with the bit trgen in the mode register (adc_mr). eoc0 govre ch0 (adc_chsr) (adc_sr) (adc_sr) adtrg eoc1 ch1 (adc_chsr) (adc_sr) ovre0 (adc_sr) undefined data data a data b adc_lcdr undefined data data a adc_cdr0 undefined data data b adc_cdr1 data c data c conversion conversion read adc_sr drdy (adc_sr) read adc_cdr1 read adc_cdr0 conversion
432 at91sam7s64 preliminary 6070a?atarm?28-oct-04 if a hardware trigger is selected, the start of a conversion is detected at each rising edge of the selected signal. if one of the tioa outputs is selected, the corresponding timer counter chan- nel must be programmed in waveform mode. only one start command is necessary to initiate a conversion sequence on all the channels. the adc hardware logic automatically performs the conversions on the active channels, then waits for a new request. the channel enable (adc_cher) and channel disable (adc_chdr) registers enable the analog channels to be enabled or disabled independently. if the adc is used with a pdc, only the transfers of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly. warning: enabling hardware triggers does not disable the software trigger functionality. thus, if a hardware trigger is selected, the start of a conversion can be initiated either by the hard- ware or the software trigger. sleep mode and conversion sequencer the adc sleep mode maximizes power saving by automatically deactivating the adc when it is not being used for conversions. sleep mode is selected by setting the bit sleep in the mode register adc_mr. the sleep mode is automatically managed by a conversion sequencer, which can automati- cally process the conversions of all channels at lowest power consumption. when a start conversion request occurs, the adc is automatically activated. as the analog cell requires a start-up time, the logic waits during this time and starts the conversion on the enabled channels. when all conversions are complete, the adc is deactivated until the next trigger. triggers occurring during the sequence are not taken into account. the conversion sequencer allows automatic processing with minimum processor intervention and optimized power consumption. conversion sequences can be performed periodically using a timer/counter output. the periodic acquisition of several samples can be processed automatically without any intervention of the processor thanks to the pdc. note: the reference voltage pins always remain connected in normal mode as in sleep mode. adc timings each adc has its own minimal startup time that is programmed through the field startup in the mode register adc_mr. in the same way, a minimal sample and hold time is necessary for the adc to guarantee the best converted final value between two channels selection. this time has to be programmed through the bitfield shtim in the mode register adc_mr. warning: no input buffer amplifier to isolate the source is included in the adc. this must be taken into consideration to program a precise value in the shtim field. see the section dc characteristics in the product datasheet.
433 at91sam7s64 preliminary 6070a?atarm?28-oct-04 analog-to-digital converter (adc) user interface table 85. adc register mapping offset register name access reset state 0x00 control register adc_cr write-only ? 0x04 mode register adc_mr read/write 0x00000000 0x08 reserved ? ? ? 0x0c reserved ? ? ? 0x10 channel enable register adc_cher write-only ? 0x14 channel disable register adc_chdr write-only ? 0x18 channel status register adc_chsr read-only 0x00000000 0x1c status register adc_sr read-only 0x000c0000 0x20 last converted data register adc_lcdr read-only 0x00000000 0x24 interrupt enable register adc_ier write-only ? 0x28 interrupt disable register adc_idr write-only ? 0x2c interrupt mask register adc_imr read-only 0x00000000 0x30 channel data register 0 adc_cdr0 read-only 0x00000000 0x34 channel data register 1 adc_cdr1 read-only 0x00000000 0x38 channel data register 2 adc_cdr2 read-only 0x00000000 0x3c channel data register 3 adc_cdr3 read-only 0x00000000 0x40 channel data register 4 adc_cdr4 read-only 0x00000000 0x44 channel data register 5 adc_cdr5 read-only 0x00000000 0x48 channel data register 6 adc_cdr6 read-only 0x00000000 0x4c channel data register 7 adc_cdr7 read-only 0x00000000 0x50 - 0xfc reserved ? ? ?
434 at91sam7s64 preliminary 6070a?atarm?28-oct-04 adc control register register name: adc_cr access type: write-only swrst: software reset 0 = no effect. 1 = resets the adc simulating a hardware reset. start: start conversion 0 = no effect. 1 = begins analog-to-digital conversion. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????? start swrst
435 at91sam7s64 preliminary 6070a?atarm?28-oct-04 adc mode register register name: adc_mr access type: read/write trgen: trigger enable trgsel: trigger selection lowres: resolution sleep: sleep mode prescal: prescaler rate selection 31 30 29 28 27 26 25 24 ???? shtim 23 22 21 20 19 18 17 16 ? ? ? startup 15 14 13 12 11 10 9 8 ?? prescal 76543210 ? ? sleep lowres trgsel trgen trgen selected trgen 0 hardware triggers are disabled. starting a conversion is only possible by software. 1 hardware trigger selected by trgsel field is enabled. trgsel selected trgsel 0 0 0 tioa ouput of the timer counter channel 0 0 0 1 tioa ouput of the timer counter channel 1 0 1 0 tioa ouput of the timer counter channel 2 011reserved 100reserved 101reserved 1 1 0 external trigger 111reserved lowres selected resolution 0 10-bit resolution 1 8-bit resolution sleep selected mode 0 normal mode 1 sleep mode
436 at91sam7s64 preliminary 6070a?atarm?28-oct-04 adcclock = mck / ( (prescal+1) * 2 ) startup: start up time startup time = (startup+1) * 8 / adcclock shtim: sample & hold time sample & hold time = (shtim+1) / adcclock
437 at91sam7s64 preliminary 6070a?atarm?28-oct-04 adc channel enable register register name: adc_cher access type: write-only chx: channel x enable 0 = no effect. 1 = enables the corresponding channel. adc channel disable register register name: adc_chdr access type: write-only chx: channel x disable 0 = no effect. 1 = disables the corresponding channel. warning: if the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conver- sion, its associated data and its corresponding eoc and ovre flags in adc_sr are unpredictable. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0
438 at91sam7s64 preliminary 6070a?atarm?28-oct-04 adc channel status register register name: adc_chsr access type: read-only chx: channel x status 0 = corresponding channel is disabled. 1 = corresponding channel is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0
439 at91sam7s64 preliminary 6070a?atarm?28-oct-04 adc status register register name: adc_sr access type: read-only eocx: end of conversion x 0 = corresponding analog channel is disabled, or the conversion is not finished. 1 = corresponding analog channel is enabled and conversion is complete. ovrex: overrun error x 0 = no overrun error on the corresponding channel since the last read of adc_sr. 1 = there has been an overrun error on the corresponding channel since the last read of adc_sr. drdy: data ready 0 = no data has been converted since the last read of adc_lcdr. 1 = at least one data has been converted and is available in adc_lcdr. govre: general overrun error 0 = no overrun error occurred since the last read of adc_sr. 1 = at least one overrun error has occurred since the last read of adc_sr. endrx: end of rx buffer 0 = the receive counter register has not reache d 0 since the last write in adc_rcr or adc_rncr. 1 = the receive counter register has reached 0 since the last write in adc_rcr or adc_rncr. rxbuff: rx buffer full 0 = adc_rcr or adc_rncr have a value other than 0. 1 = both adc_rcr and adc_rncr have a value of 0. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????rxbuffe ndrx govre drdy 15 14 13 12 11 10 9 8 ovre7 ovre6 ovre5 ovre4 ovre3 ovre2 ovre1 ovre0 76543210 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0
440 at91sam7s64 preliminary 6070a?atarm?28-oct-04 adc last converted data register register name: adc_lcdr access type: read-only ldata: last data converted the analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conver- sion is completed. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ldata 76543210 ldata
441 at91sam7s64 preliminary 6070a?atarm?28-oct-04 adc interrupt enable register register name: adc_ier access type: write-only eocx: end of conversion interrupt enable x ovrex: overrun error interrupt enable x drdy: data ready interrupt enable govre: general overrun error interrupt enable endrx: end of receive buffer interrupt enable rxbuff: receive buffer full interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????rxbuffe ndrx govre drdy 15 14 13 12 11 10 9 8 ovre7 ovre6 ovre5 ovre4 ovre3 ovre2 ovre1 ovre0 76543210 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0
442 at91sam7s64 preliminary 6070a?atarm?28-oct-04 adc interrupt disable register register name: adc_idr access type: write-only eocx: end of conversion interrupt disable x ovrex: overrun error interrupt disable x drdy: data ready interrupt disable govre: general overrun error interrupt disable endrx: end of receive buffer interrupt disable rxbuff: receive buffer full interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????rxbuffe ndrx govre drdy 15 14 13 12 11 10 9 8 ovre7 ovre6 ovre5 ovre4 ovre3 ovre2 ovre1 ovre0 76543210 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0
443 at91sam7s preliminary 6070a?atarm?28-oct-04 at91sam7s64 electrical characteristics absolute maximum ratings table 86. absolute maximum ratings* operating temperature (industrial)...... -40 c to +85 c *notice: stresses beyond those listed under ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device at these or other con- ditions beyond those indicated in the operational sections of this specification is not implied. expo- sure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ......................... -60c to +150c voltage on input pins with respect to ground .........................-0.3v to +5.5v maximum operating voltage (vddcore, and vddpll) ................................ 1.95v maximum operating voltage (vddio, vddin and vddflash)........................ 3.6v total dc output current on all i/o lines .......... 150 ma
444 at91sam7s preliminary 6070a?atarm?28-oct-04 dc characteristics the following characteristics are applicable to the operating temperature range: t a = -40c to 85c, unless otherwise spec- ified and are certified for a junction temperature up to t j = 100c. table 87. dc characteristics symbol parameter conditions min typ max units v vddcore dc supply core 1.65 1.95 v v vddpll dc supply pll 1.65 1.95 v v vddio dc supply i/os 3.0 3.6 v v vddflash dc supply flash 3.0 3.6 v v il input low-level voltage -0.3 0.8 v v ih input high-level voltage 2.0 5.5 v v ol output low-level voltage i o = 8 ma 0.4 v v oh output high-level voltage i o = 8 ma v ddio - 0.4 v i leak input leakage current pull-up resistors disabled (typ: t a = 25c, max: t a = 85c) 20 200 na i pullup input pull-up current 143 321 600 a c in input capacitance 64-lqfp package 13.9 pf i sc static current v vddcore = 1.85v, mck = 0 hz t a =25c 26 50 a all inputs driven at 1 (including tms, tdi, tck, nrst) t a = 85c 260 500 i o output current pa0-pa3 16 m a pa4-pa31 8 m a table 88. 1.8v voltage regulator characteristics symbol parameter conditions min typ max units v vddin supply voltage 3.0 3.3 3.6 v v vddout output voltage 1.81 1.85 1.89 v i vddin current consumption after startup, no load 90 a during startup, no load 100 ma idle mode 20 a t start startup time c load = 2.2 f, after v ddin > 2.7v 150 s i o maximum dc output current v ddin = 3.3v 100 ma i o maximum dc output current v ddin = 3.3v, in idle mode 1 ma
445 at91sam7s preliminary 6070a?atarm?28-oct-04 table 89. brownout detector characteristics symbol parameter conditions min typ max units v bot- threshold level 1.65 1.68 1.71 v v hyst hysteresis v hyst = v bot+ - v bot- 50 65 mv i dd current consumption bod on (gpnvm0 bit active) 12 18 a bod off (gpnvm0 bit inactive) 1 ma t start startup time 100 200 ms
446 at91sam7s preliminary 6070a?atarm?28-oct-04 power consumption typical power consumption of plls , slow clock and main oscillator. power consumption of power supply in two different modes: active and ultra low-power. power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. power consumption versus modes the values in table 90 and table 91 on page 448 are estimated values of the power con- sumption with operating conditions as follows: v ddio = v ddin = v ddflash = 3.3v v ddcore = v ddpll = 1.85v t a = 25 c mck = 50 mhz there is no consumption on the i/os of the device figure 188. measure schematics: 1.8v vddin voltage regulator vddout vddcore vddpll 3.3v vddio vddflash amp1 amp2
447 at91sam7s preliminary 6070a?atarm?28-oct-04 these figures represent the power consum ption estimated on the power supplies.. table 90. power consumption for different modes mode conditions consumption unit active voltage regulator is on. brown out detector is activated. flash is read. arm core clock is 50mhz. analog-to-digital converter activated. all peripheral clocks activated. onto amp1 onto amp2 31.3 29.3 ma ultra low power voltage regulator is in low-power mode. brown out detector is de-activated. flash is in standby mode. arm core clock is 500hz. analog-to-digital converter de-activated. all peripheral clocks de-activated. onto amp1 onto amp2 36.2 35.2 a
448 at91sam7s preliminary 6070a?atarm?28-oct-04 peripheral power consumption in active mode table 91. power consumption by peripheral peripheral consumption unit pio controller 0.4 ma usart 0.9 adc 0.7 pwm 0.3 twi 0.2 spi 0.9 ssc 1.1 timer counter channels 0.2
449 at91sam7s preliminary 6070a?atarm?28-oct-04 power consumption versus master clock frequency in active mode figure 189 produces estimated values with operating conditions as follows: v ddio = v ddin = v ddflash = 3.3v v ddcore = v ddpll = 1.85v t a = 25 c mck in the mhz range voltage regulator is on brown-out detector is activated flash is read analog-to-digital converter activated all peripheral clocks activated there is no consumption on the i/os of the device figure 189 presents the power consumption estimated on the power supply. figure 189. power consumption versus mck frequency in active mode current consumption at 3.3v 31,278 16,219 8,685 4,918 3,035 2,063 1,622 100 1,000 10,000 100,000 50 25 12.5 6.25 3.125 1.5625 0.78125 frequency (mhz) consumption (a )
450 at91sam7s preliminary 6070a?atarm?28-oct-04 power consumption versus master clock frequency in ultra low-power mode figure 190 produces estimated values with operating conditions as follows: v ddio = v ddin = v ddflash = 3.3v v ddcore = v ddpll = 1.85v t a = 25 c voltage regulator is in low-power mode brown out detector is de-activated flash is in standby mode analog-to-digital converter de-activated all peripheral clocks de-activated pll in standby main oscillator in standby there is no consumption on the i/os of the device figure 190 presents the power consumption estimated on the power supply. figure 190. power consumption versus mck frequency in the ultra low power mode current consumption at 3.3v 46 40.5 37.7 36.4 35.7 35.3 35.2 10 100 32 16 8 4 2 1 0.5 frequency (khz) consumption (a )
451 at91sam7s preliminary 6070a?atarm?28-oct-04 crystal oscillators characteristics rc oscillator characteristics main oscillator characteristics notes: 1. c s is the shunt capacitance xin clock characteristics note: 1. these characteristics apply only when the main oscillat or is in bypass mode (i.e., when moscen = 0 and oscbypass = 1 in the ckgr_mor register, see ?pmc clock generator main oscillator register? on page 171). table 92. rc oscillator characteristics symbol parameter conditions min typ max unit 1/(t cprc ) rc oscillator frequency v ddpll = 1.65v 22 32 42 khz duty cycle 45 50 55 % t st startup time v ddpll = 1.65v 75 s i osc current consumption after startup time 1.9 a table 93. main oscillator characteristics symbol parameter conditions min typ max unit 1/(t cpmain ) crystal oscillator frequency 3 16 20 mhz c l1 , c l2 internal load capacitance (c l1 = c l2 ) 25 pf c l equivalent load capacitance 12.5 pf duty cycle 40 50 60 % t st startup time v ddpll = 1.2 to 2v c s = 3 pf (1) 1/(t cpmain ) = 3 mhz c s = 7 pf (1) 1/(t cpmain ) = 16 mhz c s = 7 pf (1) 1/(t cpmain ) = 20 mhz 14.5 1.4 1 ms i osc current consumption active mode 550 a standby mode 1 a table 94. xin clock electrical characteristics symbol parameter conditions min max units 1/(t cpxin ) xin clock frequency 50.0 mhz t cpxin xin clock period 20.0 ns t chxin xin clock high half-period 0.4 x t cpxin 0.6 x t cpxin t clxin xin clock low half-period 0.4 x t cpxin 0.6 x t cpxin c in xin input capacitance (1) 25 pf r in xin pull-down resistor (1) 500 k ?
452 at91sam7s preliminary 6070a?atarm?28-oct-04 pll characteristics note: startup time depends on pll rc filter. a calculation tool is provided by atmel. table 95. phase lock loop characteristics symbol parameter conditions min typ max unit f out output frequency field out of ckgr_pll is: 00 80 160 mhz 10 150 220 mhz f in input frequency 1 32 mhz i pll current consumption active mode 4 ma standby mode 1 a
453 at91sam7s preliminary 6070a?atarm?28-oct-04 adc characteristics table 96. channel conversion time and adc clock parameter conditions min typ max units adc clock frequency 5mhz startup time return from idle mode 20 s track and hold acquisition time 600 ns conversion time adc clock = 5 mhz 2 s throughput rate adc clock = 5 mhz 384 ksps table 97. external voltage reference input parameter conditions min max units advref input voltage range 2.6 v ddin v advref average current on 13 samples with adc clock = 5 mhz 12 250 a table 98. analog inputs parameter min typ max units input voltage range 0v advref input leakage current 1a input capacitance 12 14 pf table 99. transfer characteristics parameter conditions min typ max units resolution 10 bit integral non-linearity 2 lsb adc clock = 5 mhz 3 lsb differential non-linearity 1 lsb adc clock = 5 mhz 2 lsb offset error 2 lsb gain error 2 lsb
454 at91sam7s preliminary 6070a?atarm?28-oct-04 at91sam7s64 ac characteristics applicable conditions and derating data these conditions and derating process apply to the following paragraphs: clock characteris- tics, embedded flash characteristics and jtag/ice timings. conditions and timings computation all delays are given as typical values under the following conditions: v ddio = 3.3v v ddcore = 1.8v ambient temperature = 25c load capacitance = 0 pf the output level change detection is (0.5 x v ddio ). the input level is 0.8v for a low-level detection and is 2.0v for a high-level detection. the minimum and maximum values given in the ac characteristics tables of this datasheet take into account process variation and design. in order to obtain the timing for other condi- tions, the following equation should be used: where: t is the derating factor in temperature given in figure 191 on page 455. vddcore is the derating factor for the core power supply given in figure 192 on page 455. t datasheet is the minimum or maximum timing value given in this datasheet for a load capacitance of 0 pf. vddio is the derating factor for the io power supply given in figure 193 on page 456. c signa l is the capacitance load on the considered output pin (1) . csignal is the load derating factor depending on the capacitance load on the related output pins given in min and max in this datasheet. the input delays are given as typical values. note: the user must take into account the package capacitance load contribution (c in ) described in table 87, ?dc characteristics,? on page 444. t t vddcore t datasheet () vddio c signal csignal () () + () =
455 at91sam7s preliminary 6070a?atarm?28-oct-04 temperature derating factor figure 191. derating curve for different operating temperatures v ddcore voltage derating factor figure 192. derating curve for different core supply voltages 0,85 0,9 0,95 1 1,05 1,1 -40-30-20-10 0 1020304050607080 operating temperature (c) derating factor 0,8 0,85 0,9 0,95 1 1,05 1,1 1,15 1,2 1,65 1,7 1,75 1,8 1,85 1,9 1,95 core supply voltage (v) derating factor
456 at91sam7s preliminary 6070a?atarm?28-oct-04 v ddio voltage derating factor figure 193. derating curve for different io supply voltages note: the derating factor in this example is applicable only to timings related to output pins. 0,85 0,9 0,95 1 1,05 1,1 1,15 3 3,1 3,2 3,3 3,4 3,5 3,6 i/o supply voltage (v ) derating factor
457 at91sam7s preliminary 6070a?atarm?28-oct-04 clock characteristics these parameters are given in the following conditions: v ddcore = 1.8v ambient temperature = 25c the temperature derating factor described in ?applicable conditions and derating data? on page 454 and ?vddcore voltage derating factor? on page 455 are both applicable to these characteristics. master clock characteristics table 100. master clock waveform parameters symbol parameter conditions min max units 1/(t cpmck ) master clock frequency 73 mhz
458 at91sam7s preliminary 6070a?atarm?28-oct-04 embedded flash characteristics the maximum operating frequency is given in table 101 but is limited by the embedded flash access time when the pro- cessor is fetching code out of it. table 102 gives the device maximum operating frequency depending on the field fws of the mc_fmr register. this field defines the number of wait states required to access the embedded flash memory. table 101. dc flash characteristics symbol parameter conditions min max units t pu power-up delay 30 s i sb standby current @85c onto vddcore = 1.8v onto vddflash = 3.3v 0 30 a i cc active current random read @ 40mhz onto vddcore = 1.8v onto vddflash = 3.3v 5.0 1.0 ma write onto vddcore = 1.8v onto vddflash = 3.3v 500 8.0 a ma table 102. embedded flash wait states fws read operations maximum operating frequency (mhz) 0 1 cycle 40 1 2 cycles 1/(t cpmck ) 2 3 cycles 1/(t cpmck ) 3 4 cycles 1/(t cpmck ) table 103. ac flash characteristics parameter conditions min max units program cycle time per page including auto-erase 4 ms per page without auto-erase 2 ms full chip erase 10 ms
459 at91sam7s preliminary 6070a?atarm?28-oct-04 jtag/ice timings ice interface signals table 104 shows timings relative to operating condition limits defined in the section ?condi- tions and timings computation? on page 454. figure 194. ice interface signals table 104. ice interface timing specification symbol parameter conditions min max units ice 0 tck low half-period 51 ns ice 1 tck high half-period 51 ns ice 2 tck period 102 ns ice 3 tdi, tms, setup before tck high 3 ns ice 4 tdi, tms, hold after tck high 0 ns ice 5 tdo hold time c tdo = 0 pf 3 ns c tdo derating 0.037 ns/pf ice 6 tck low to tdo valid c tdo = 0 pf 13 ns c tdo derating 0.037 ns/pf tck ice 3 ice 4 ice 6 tms/tdi tdo ice 5 ice 1 ice 2 ice 0
460 at91sam7s preliminary 6070a?atarm?28-oct-04 jtag interface signals the following table shows timings relative to operating condition limits defined in the section ?conditions and timings computation? on page 454. table 105. jtag interface timing specification symbol parameter conditions min max units jtag 0 tck low half-period 6.5 ns jtag 1 tck high half-period 5.5 ns jtag 2 tck period 12 ns jtag 3 tdi, tms setup before tck high 2 ns jtag 4 tdi, tms hold after tck high 3 ns jtag 5 tdo hold time c tdo = 0 pf 2 ns c tdo derating 0.037 ns/pf jtag 6 tck low to tdo valid c tdo = 0 pf 15 ns c tdo derating 0.037 ns/pf jtag 7 device inputs setup time 0 ns jtag 8 device inputs hold time 3 ns jtag 9 device outputs hold time c out = 0 pf 4 ns c out derating 0.037 ns/pf jtag 10 tck to device outputs valid c out = 0 pf 20 ns c out derating 0.037 ns/pf
461 at91sam7s preliminary 6070a?atarm?28-oct-04 figure 195. jtag interface signals tck jtag 9 tms/tdi tdo device outputs jtag 5 jtag 4 jtag 3 jtag 0 jtag 1 jtag 2 jtag 10 device inputs jtag 8 jtag 7 jtag 6
462 at91sam7s preliminary 6070a?atarm?28-oct-04 at91sam7s64 mechanical characteristics thermal considerations thermal data in table 106, the device lifetime is estimated using the mil-217 standard in the ?moderately controlled? environmental model (this model is described as corresponding to an installation in a permanent rack with adequate cooling air), depending on the device junction temperature. (for details see the section ?junction temperature? on page 463.) note that the user must be extremely cautious with this mtbf calculation. it should be noted that the mil-217 model is pessimistic with respect to observed values due to the way the data/models are obtained (test under severe conditions). the life test results that have been measured are always better than the predicted ones. table 107 summarizes the thermal resistance data depending on the package. table 106. mtbf versus junction temperature junction temperature (t j ) (c) estimated lifetime (mtbf) (year) 100 17 125 9 150 5 175 3 table 107. thermal resistance data symbol parameter condition package typ unit ja junction-to-ambient thermal resistance still air lqfp64 47.2 c/w jc junction-to-case thermal resistance lqfp64 12.2
463 at91sam7s preliminary 6070a?atarm?28-oct-04 junction temperature the average chip-junction temperature, t j , in c can be obtained from the following: 4. 5. where: ja = package thermal resistance, junction-to-ambient (c/w), provided in table 107 on page 462. jc = package thermal resistance, junction-to-case thermal resistance (c/w), provided in table 107 on page 462. heat sink = cooling device thermal resistance (c/w), provided in the device datasheet. p d = device power consumption (w) estimated from data provided in the section ?power consumption? on page 446. t a = ambient temperature (c). from the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. if a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature t j in c. package drawings figure 196. 64-lead lqfp package drawing t j t a p d ja () + = t j t a p ( d ( heatsink jc )) ++ =
464 at91sam7s preliminary 6070a?atarm?28-oct-04 table 108. 64-lead lqfp package dimensions (in mm) table 109. device and 64-lead lqfp package maximum weight 700 mg table 110. 64-lead lqfp package characteristics moisture sensitivity level 3
465 at91sam7s preliminary 6070a?atarm?28-oct-04 soldering profile table 111 gives the recommended soldering profile from j-std-20. small packages may be subject to higher temperatures if they are reflowed in boards with larger components. in this case, small packages may have to withstand temperatures of up to 235 c, not 220 c (ir reflow). recommended package reflow conditions depend on package thickness and volume. see table 112. when certain small thin packages are used on boards without larger packages, these small packages may be classified at 220c instead of 235c. notes: 1. the packages are qualified by atmel by using ir reflow conditions, not convection or vpr. 2. by default, the package level 1 is qualified at 220 c (unless 235 c is stipulated). 3. the body temperature is the most important parameter but other profile parameters such as total exposure time to hot temperature or heating rate may also influence component reliability. a maximum of three reflow passes is allowed per component. table 111. soldering profile convection or ir/convection vpr average ramp-up rate (183 c to peak) 3 c/sec. max. 10 c/sec. preheat temperature 125 c 25 c 120 sec. max temperature maintained above 183 c 60 sec. to 150 sec. time within 5 c of actual peak temperature 10 sec. to 20 sec. 60 sec. peak temperature range 220 +5/-0 c or 235 +5/-0 c 215 to 219 c or 235 +5/-0 c ramp-down rate 6 c/sec. 10 c/sec. time 25 c to peak temperature 6 min. max table 112. recommended package reflow conditions (1, 2, 3) parameter temperature convection 235 +5/-0 c vpr 235 +5/-0 c ir/convection 235 +5/-0 c
466 at91sam7s preliminary 6070a?atarm?28-oct-04 at91sam7s64 ordering information table 113. ordering information ordering code package temperature operating range AT91SAMS64-AI lqfp 64 industrial (-40c to 85c)
i at91sam7s64 preliminary 6070a?atarm?28-oct-04 table of contents features............................................................................................................... 1 description .......................................................................................................... 2 block diagram..................................................................................................... 3 signal description .............................................................................................. 4 package and pinout............................................................................................ 7 64-lead lqfp mechanical overview................................................................ 7 pinout ............................................................................................................... 7 power considerations........................................................................................ 8 power supplies ................................................................................................ 8 power consumption......................................................................................... 8 voltage regulator ............................................................................................ 8 typical powering schematics .......................................................................... 9 i/o lines considerations ................................................................................. 10 jtag port pins .............................................................................................. 10 test pin .......................................................................................................... 10 reset pin........................................................................................................ 10 erase pin..................................................................................................... 10 pio controller a lines ................................................................................... 10 i/o line drive levels...................................................................................... 10 processor and architecture............................................................................. 11 arm7tdmi processor ................................................................................... 11 debug and test features .............................................................................. 11 memory controller.......................................................................................... 11 peripheral data controller.............................................................................. 12 memory .............................................................................................................. 13 memory mapping ........................................................................................... 13 embedded flash ............................................................................................ 14 fast flash programming interface................................................................. 15 system controller............................................................................................. 16 system controller mapping............................................................................ 17 reset controller ............................................................................................. 18 clock generator ............................................................................................. 19 power management controller ...................................................................... 20 advanced interrupt controller ........................................................................ 20 debug unit ..................................................................................................... 21 periodic interval timer ................................................................................... 21 watchdog timer............................................................................................. 21 real-time timer.............................................................................................. 21 pio controller ................................................................................................ 21 voltage regulator controller.......................................................................... 22 peripherals ........................................................................................................ 23 peripheral mapping ........................................................................................ 23 peripheral multiplexing on pio lines ............................................................. 24 pio controller a multiplexing ......................................................................... 25 peripheral identifiers ...................................................................................... 26 serial peripheral interface.............................................................................. 26
ii at91sam7s64 preliminary 6070a?atarm?28-oct-04 two-wire interface.......................................................................................... 27 usart ........................................................................................................... 27 serial synchronous controller ....................................................................... 27 timer counter ................................................................................................ 27 pwm controller.............................................................................................. 28 usb device port ............................................................................................ 28 analog-to-digital converter ............................................................................ 28 arm7tdmi processor overview .................................................................. 31 overview............................................................................................................ 31 arm7tdmi processor ...................................................................................... 32 instruction type.............................................................................................. 32 data type....................................................................................................... 32 arm7tdmi operating mode.......................................................................... 32 arm7tdmi registers .................................................................................... 32 arm instruction set overview ....................................................................... 34 thumb instruction set overview .................................................................... 35 at91sam7s64 debug and test features ................................................... 37 description ........................................................................................................ 37 block diagram................................................................................................... 37 application examples ...................................................................................... 38 debug environment ....................................................................................... 38 test environment ........................................................................................... 39 debug and test pin description ..................................................................... 39 functional description..................................................................................... 40 test pin.............................................................................................................. 40 embedded in-circuit emulator ........................................................................ 40 debug unit ..................................................................................................... 40 ieee 1149.1 jtag boundary scan ............................................................... 40 id code register............................................................................................ 44 reset controller (rstc) ............................................................................... 45 overview............................................................................................................ 45 block diagram................................................................................................... 45 functional description..................................................................................... 46 nrst manager .............................................................................................. 46 brownout manager ......................................................................................... 47 reset states................................................................................................... 48 reset state priorities ..................................................................................... 53 reset controller status register.................................................................... 53 reset controller (rstc) user interface.......................................................... 55 reset controller control register .................................................................. 56 reset controller status register.................................................................... 57 reset controller mode register..................................................................... 58
iii at91sam7s64 preliminary 6070a?atarm?28-oct-04 real-time timer (rtt) ................................................................................... 59 overview............................................................................................................ 59 block diagram................................................................................................... 59 functional description..................................................................................... 60 real-time timer (rtt) user interface ............................................................. 62 real-time timer mode register ..................................................................... 63 real-time timer alarm register..................................................................... 64 real-time timer value register ..................................................................... 65 real-time timer status register .................................................................... 66 periodic interval timer (pit)......................................................................... 67 overview............................................................................................................ 67 block diagram................................................................................................... 67 functional description..................................................................................... 68 periodic interval timer (pit) user interface ................................................... 70 periodic interval timer mode register........................................................... 71 periodic interval timer status register.......................................................... 72 periodic interval timer value register........................................................... 73 periodic interval timer image register.......................................................... 74 watchdog timer (wdt) ................................................................................. 75 overview............................................................................................................ 75 block diagram................................................................................................... 75 functional description..................................................................................... 76 watchdog timer (wdt) user interface ........................................................... 78 watchdog timer control register.................................................................. 79 watchdog timer mode register .................................................................... 80 watchdog timer status register ................................................................... 81 voltage regulator mode controller (vreg)................................................ 83 overview............................................................................................................ 83 voltage regulator power controller (vreg) user interface ........................ 83 voltage regulator mode register .................................................................. 83 memory controller (mc)................................................................................ 85 overview............................................................................................................ 85 block diagram................................................................................................... 85 functional description..................................................................................... 86 bus arbiter ..................................................................................................... 86 address decoder ........................................................................................... 86 remap command .......................................................................................... 87 abort status ................................................................................................... 88 embedded flash controller ........................................................................... 88 misalignment detector ................................................................................... 88
iv at91sam7s64 preliminary 6070a?atarm?28-oct-04 memory controller (mc) user interface.......................................................... 89 mc remap control register .......................................................................... 90 mc abort status register .............................................................................. 91 mc abort address status register ................................................................ 92 embedded flash controller (efc) ............................................................... 93 overview............................................................................................................ 93 functional description..................................................................................... 93 embedded flash organization....................................................................... 93 read operations ............................................................................................ 95 write operations ............................................................................................ 97 flash commands ........................................................................................... 97 embedded flash controller (efc) user interface ....................................... 102 mc flash mode register ............................................................................. 103 mc flash command register ...................................................................... 104 mc flash status register ............................................................................ 106 fast flash programming interface (ffpi) ................................................. 107 overview.......................................................................................................... 107 parallel fast flash programming.................................................................. 108 device configuration.................................................................................... 108 signal names............................................................................................... 109 entering programming mode ....................................................................... 110 read handshaking....................................................................................... 111 device operations........................................................................................ 112 serial fast flash programming..................................................................... 116 device configuration.................................................................................... 116 entering serial programming mode ............................................................. 117 read/write handshake ................................................................................ 117 device operations........................................................................................ 118 peripheral data controller (pdc) ............................................................... 121 overview.......................................................................................................... 121 block diagram................................................................................................. 121 functional description................................................................................... 122 configuration................................................................................................ 122 memory pointers .......................................................................................... 122 transfer counters ........................................................................................ 122 data transfers ............................................................................................. 123 priority of pdc transfer requests ............................................................... 123 peripheral data controller (pdc) user interface ......................................... 124 pdc receive pointer register..................................................................... 125 pdc receive counter register ................................................................... 125 pdc transmit pointer register.................................................................... 126 pdc transmit counter register .................................................................. 126
v at91sam7s64 preliminary 6070a?atarm?28-oct-04 pdc receive next pointer register ............................................................ 127 pdc receive next counter register ........................................................... 127 pdc transmit next pointer register ........................................................... 128 pdc transmit next counter register .......................................................... 128 pdc transfer control register .................................................................... 129 pdc transfer status register...................................................................... 130 advanced interrupt controller (aic) .......................................................... 131 overview.......................................................................................................... 131 block diagram................................................................................................. 131 application block diagram ............................................................................ 131 aic detailed block diagram .......................................................................... 132 i/o line description........................................................................................ 132 product dependencies................................................................................... 132 i/o lines....................................................................................................... 132 power management ..................................................................................... 132 interrupt sources.......................................................................................... 132 functional description................................................................................... 134 interrupt source control............................................................................... 134 interrupt latencies ....................................................................................... 136 normal interrupt ........................................................................................... 137 fast interrupt................................................................................................ 139 protect mode................................................................................................ 142 spurious interrupt......................................................................................... 143 general interrupt mask ................................................................................ 143 advanced interrupt controller (aic) user interface .................................... 144 base address............................................................................................... 144 aic source mode register .......................................................................... 145 aic source vector register ......................................................................... 146 aic interrupt vector register ....................................................................... 146 aic fiq vector register ...................................................................................... 147 aic interrupt status register ....................................................................... 148 aic interrupt pending register .................................................................... 148 aic interrupt mask register......................................................................... 149 aic core interrupt status register .............................................................. 149 aic interrupt enable command register..................................................... 150 aic interrupt disable command register.................................................... 150 aic interrupt clear command register ....................................................... 151 aic interrupt set command register .......................................................... 151 aic end of interrupt command register ..................................................... 152 aic spurious interrupt vector register........................................................ 152 aic debug control register......................................................................... 153 aic fast forcing enable register................................................................ 153 aic fast forcing disable register............................................................... 154 aic fast forcing status register................................................................. 154
vi at91sam7s64 preliminary 6070a?atarm?28-oct-04 clock generator........................................................................................... 155 description ...................................................................................................... 155 slow clock rc oscillator ............................................................................. 155 main oscillator ............................................................................................. 155 divider and pll block.................................................................................. 157 power management controller (pmc) ....................................................... 158 description ................................................................................................... 158 master clock controller................................................................................ 158 processor clock controller .......................................................................... 158 usb clock controller ................................................................................... 159 peripheral clock controller .......................................................................... 159 programmable clock output controller ....................................................... 159 programming sequence .............................................................................. 160 clock switching details................................................................................ 163 power management controller (pmc) user interface ................................ 166 debug unit (dbgu) ..................................................................................... 179 overview.......................................................................................................... 179 block diagram................................................................................................. 180 product dependencies................................................................................... 181 i/o lines....................................................................................................... 181 power management ..................................................................................... 181 interrupt source ........................................................................................... 181 uart operations............................................................................................ 181 baud rate generator ................................................................................... 181 receiver ....................................................................................................... 182 transmitter ................................................................................................... 184 peripheral data controller............................................................................ 185 test modes .................................................................................................. 185 debug communication channel support..................................................... 186 chip identifier ............................................................................................... 187 ice access prevention ................................................................................ 187 debug unit user interface ............................................................................. 188 debug unit control register ........................................................................ 189 debug unit mode register ........................................................................... 190 debug unit interrupt enable register .......................................................... 191 debug unit interrupt disable register ......................................................... 192 debug unit interrupt mask register............................................................. 193 debug unit status register.......................................................................... 194 debug unit receiver holding register ........................................................ 196 debug unit transmit holding register......................................................... 197 debug unit baud rate generator register.................................................. 197 debug unit chip id register........................................................................ 198
vii at91sam7s64 preliminary 6070a?atarm?28-oct-04 debug unit chip id extension register ....................................................... 201 debug unit force ntrst register.............................................................. 201 parallel input/output controller (pio) ....................................................... 203 overview.......................................................................................................... 203 block diagram................................................................................................. 204 application block diagram ............................................................................ 204 product dependencies................................................................................... 205 pin multiplexing ............................................................................................ 205 external interrupt lines ................................................................................ 205 power management ..................................................................................... 205 interrupt generation ..................................................................................... 205 functional description................................................................................... 206 pull-up resistor control ............................................................................... 206 i/o line or peripheral function selection .................................................... 207 peripheral a or b selection .......................................................................... 207 output control.............................................................................................. 207 synchronous data output............................................................................ 208 multi drive control (open drain).................................................................. 208 output line timings ..................................................................................... 208 inputs ........................................................................................................... 208 input glitch filtering ..................................................................................... 209 input change interrupt ................................................................................. 209 i/o lines programming example .................................................................. 211 parallel input/output controller (pio) user interface.................................. 212 pio controller pio enable register............................................................. 214 pio controller pio disable register............................................................ 214 pio controller pio status register.............................................................. 215 pio controller output enable register ........................................................ 215 pio controller output disable register ....................................................... 216 pio controller output status register ......................................................... 216 pio controller input filter enable register .................................................. 217 pio controller input filter disable register ................................................. 217 pio controller input filter status register................................................... 218 pio controller set output data register ..................................................... 218 pio controller clear output data register .................................................. 219 pio controller output data status register ................................................ 219 pio controller pin data status register ...................................................... 220 pio controller interrupt enable register ..................................................... 220 pio controller interrupt disable register..................................................... 221 pio controller interrupt mask register ........................................................ 221 pio controller interrupt status register ...................................................... 222 pio multi-driver enable register.................................................................. 222 pio multi-driver disable register................................................................. 223 pio multi-driver status register................................................................... 223 pio pull up disable register ....................................................................... 224
viii at91sam7s64 preliminary 6070a?atarm?28-oct-04 pio pull up enable register........................................................................ 224 pio pull up status register......................................................................... 225 pio peripheral a select register................................................................. 225 pio peripheral b select register................................................................. 226 pio peripheral a b status register ............................................................. 226 pio output write enable register ............................................................... 227 pio output write disable register .............................................................. 227 pio output write status register ................................................................ 228 serial peripheral interface (spi) ................................................................. 229 overview.......................................................................................................... 229 block diagram................................................................................................. 230 application block diagram ............................................................................ 230 signal description ......................................................................................... 231 product dependencies................................................................................... 231 i/o lines....................................................................................................... 231 power management ..................................................................................... 231 interrupt........................................................................................................ 231 functional description................................................................................... 232 modes of operation...................................................................................... 232 data transfer ............................................................................................... 232 master mode operations.............................................................................. 234 spi slave mode ........................................................................................... 239 serial peripheral interface (spi) user interface .......................................... 241 spi control register .................................................................................... 242 spi mode register ....................................................................................... 243 spi receive data register .......................................................................... 245 spi transmit data register ......................................................................... 246 spi status register...................................................................................... 247 spi interrupt enable register ...................................................................... 249 spi interrupt disable register...................................................................... 250 spi interrupt mask register ......................................................................... 251 spi chip select register.............................................................................. 252 two-wire interface (twi) ............................................................................. 255 overview.......................................................................................................... 255 block diagram................................................................................................. 255 application block diagram ............................................................................ 255 product dependencies................................................................................... 256 i/o lines description.................................................................................... 256 power management ..................................................................................... 256 interrupt........................................................................................................ 256 functional description................................................................................... 257 transfer format ........................................................................................... 257 modes of operation...................................................................................... 257
ix at91sam7s64 preliminary 6070a?atarm?28-oct-04 transmitting data......................................................................................... 257 read/write flowcharts................................................................................. 260 two-wire interface (twi) user interface ...................................................... 262 twi control register.................................................................................... 263 twi master mode register .......................................................................... 264 twi internal address register ..................................................................... 265 twi clock waveform generator register.................................................... 265 twi status register ..................................................................................... 266 twi interrupt enable register...................................................................... 267 twi interrupt disable register..................................................................... 268 twi interrupt mask register ........................................................................ 269 twi receive holding register ..................................................................... 270 twi transmit holding register .................................................................... 270 universal synchronous/asynchronous receiver/transmitter (usart) 271 overview.......................................................................................................... 271 block diagram................................................................................................. 272 application block diagram ............................................................................ 273 i/o lines description ..................................................................................... 273 product dependencies................................................................................... 274 i/o lines....................................................................................................... 274 power management ..................................................................................... 274 interrupt........................................................................................................ 274 functional description................................................................................... 275 baud rate generator ................................................................................... 275 receiver and transmitter control ................................................................ 279 synchronous and asynchronous modes...................................................... 279 iso7816 mode ............................................................................................. 289 irda mode .................................................................................................... 291 rs485 mode ................................................................................................ 294 modem mode ............................................................................................... 295 test modes .................................................................................................. 296 usart user interface ................................................................................... 298 usart control register .............................................................................. 299 usart mode register................................................................................. 301 usart interrupt enable register ................................................................ 304 usart interrupt disable register ............................................................... 305 usart interrupt mask register................................................................... 306 usart channel status register ................................................................. 307 usart receive holding register ............................................................... 309 usart transmit holding register .............................................................. 309 usart baud rate generator register ....................................................... 310 usart receiver time-out register ............................................................ 311 usart transmitter timeguard register ..................................................... 312 usart fi di ratio register...................................................................... 313 usart number of errors register .............................................................. 314
x at91sam7s64 preliminary 6070a?atarm?28-oct-04 usart irda filter register ..................................................................... 314 synchronous serial controller (ssc)........................................................ 315 overview.......................................................................................................... 315 block diagram................................................................................................. 315 application block diagram ............................................................................ 316 pin name list .................................................................................................. 317 product dependencies................................................................................... 317 i/o lines....................................................................................................... 317 power management ..................................................................................... 317 interrupt........................................................................................................ 317 functional description................................................................................... 317 clock management ...................................................................................... 318 clock divider ................................................................................................ 319 transmitter operations ................................................................................ 321 receiver operations .................................................................................... 322 start.............................................................................................................. 322 frame sync.................................................................................................. 324 data format ................................................................................................. 324 loop mode ................................................................................................... 326 interrupt........................................................................................................ 326 ssc application examples ............................................................................ 328 synchronous serial controller (ssc) user interface ................................. 330 ssc control register................................................................................... 331 ssc clock mode register ........................................................................... 331 ssc receive clock mode register ............................................................. 332 ssc receive frame mode register ............................................................ 334 ssc transmit clock mode register ............................................................ 336 ssc transmit frame mode register ........................................................... 338 ssc receive holding register .................................................................... 340 ssc transmit holding register ................................................................... 340 ssc receive synchronization holding register.......................................... 341 ssc transmit synchronization holding register......................................... 341 ssc status register .................................................................................... 342 ssc interrupt enable register..................................................................... 344 ssc interrupt disable register .................................................................... 345 ssc interrupt mask register ....................................................................... 346 timer/counter (tc)...................................................................................... 347 overview.......................................................................................................... 347 block diagram................................................................................................. 347 pin name list .................................................................................................. 348 product dependencies................................................................................... 348 i/o lines....................................................................................................... 348 power management ..................................................................................... 348
xi at91sam7s64 preliminary 6070a?atarm?28-oct-04 interrupt........................................................................................................ 348 functional description................................................................................... 348 tc description ............................................................................................. 348 capture operating mode.............................................................................. 351 waveform operating mode .......................................................................... 353 timer/counter (tc) user interface ................................................................ 360 global register mapping ............................................................................. 360 channel memory mapping ........................................................................... 360 tc block control register............................................................................ 361 tc block mode register .............................................................................. 361 tc channel control register ....................................................................... 362 tc channel mode register: capture mode................................................. 363 tc channel mode register: waveform mode ............................................. 365 tc counter value register .......................................................................... 368 tc register a............................................................................................... 368 tc register b............................................................................................... 369 tc register c .............................................................................................. 369 tc status register....................................................................................... 370 tc interrupt enable register ....................................................................... 372 tc interrupt disable register....................................................................... 373 tc interrupt mask register .......................................................................... 374 pulse width modulation controller (pwm) ............................................... 375 overview.......................................................................................................... 375 block diagram................................................................................................. 375 i/o lines description...................................................................................... 376 product dependencies................................................................................... 376 i/o lines....................................................................................................... 376 power management ..................................................................................... 376 interrupt sources.......................................................................................... 376 functional description................................................................................... 377 pwm clock generator ................................................................................. 377 pwm channel .............................................................................................. 378 pwm controller operations ......................................................................... 382 pwm user interface ........................................................................................ 384 pwm register mapping ............................................................................... 384 pwm mode register .................................................................................... 385 pwm enable register.................................................................................. 386 pwm disable register ................................................................................. 386 pwm status register................................................................................... 387 pwm interrupt enable register ................................................................... 388 pwm interrupt disable register................................................................... 388 pwm interrupt mask register ...................................................................... 389 pwm interrupt status register .................................................................... 389 pwm channel mode register...................................................................... 390 pwm channel duty cycle register ............................................................. 391
xii at91sam7s64 preliminary 6070a?atarm?28-oct-04 pwm channel period register .................................................................... 392 pwm channel counter register.................................................................. 393 pwm channel update register ................................................................... 393 pwm version register................................................................................. 394 usb device port (udp) ............................................................................... 395 overview.......................................................................................................... 395 block diagram................................................................................................. 395 product dependencies................................................................................... 396 i/o lines....................................................................................................... 396 power management ..................................................................................... 396 interrupt........................................................................................................ 396 typical connection......................................................................................... 397 functional description................................................................................... 398 usb v2.0 full-speed introduction................................................................ 398 handling transactions with usb v2.0 device peripheral............................ 399 controlling device states............................................................................. 409 usb device port (udp) user interface ......................................................... 411 usb frame number register ...................................................................... 412 usb global state register........................................................................... 413 usb function address register .................................................................. 414 usb interrupt enable register..................................................................... 415 usb interrupt disable register .................................................................... 416 usb interrupt mask register ....................................................................... 417 usb interrupt status register...................................................................... 418 usb interrupt clear register ....................................................................... 420 usb reset endpoint register ...................................................................... 421 usb endpoint control and status register ................................................. 422 usb fifo data register.............................................................................. 425 usb transceiver control register ............................................................... 426 analog-to-digital converter (adc) ............................................................. 427 overview.......................................................................................................... 427 block diagram................................................................................................. 427 signal description .......................................................................................... 428 product dependencies................................................................................... 428 power management ..................................................................................... 428 interrupt sources.......................................................................................... 428 analog inputs ............................................................................................... 428 i/o lines....................................................................................................... 428 timer triggers .............................................................................................. 428 conversion performances............................................................................ 428 functional description................................................................................... 429 analog-to-digital conversion ........................................................................ 429 conversion reference ................................................................................. 429
xiii at91sam7s64 preliminary 6070a?atarm?28-oct-04 conversion resolution ................................................................................. 429 conversion results ...................................................................................... 429 conversion triggers..................................................................................... 431 sleep mode and conversion sequencer ..................................................... 432 adc timings ................................................................................................ 432 analog-to-digital converter (adc) user interface ....................................... 433 adc control register................................................................................... 434 adc mode register ..................................................................................... 435 adc channel enable register..................................................................... 437 adc channel disable register.................................................................... 437 adc channel status register...................................................................... 438 adc status register .................................................................................... 439 adc last converted data register ............................................................. 440 adc interrupt enable register..................................................................... 441 adc interrupt disable register.................................................................... 442 at91sam7s64 electrical characteristics ................................................. 443 absolute maximum ratings........................................................................... 443 dc characteristics.......................................................................................... 444 power consumption....................................................................................... 446 power consumption versus modes ............................................................. 446 peripheral power consumption in active mode........................................... 448 power consumption versus master clock frequency in active mode......... 449 power consumption versus master clock frequency in ultra low-power mode ................................................................................. 450 crystal oscillators characteristics ............................................................... 451 rc oscillator characteristics ....................................................................... 451 main oscillator characteristics..................................................................... 451 xin clock characteristics ............................................................................ 451 pll characteristics ........................................................................................ 452 adc characteristics ................. ..................................................................... 453 at91sam7s64 ac characteristics ............................................................ 454 applicable conditions and derating data .................................................... 454 conditions and timings computation .......................................................... 454 temperature derating factor....................................................................... 455 vddcore voltage derating factor ............................................................ 455 vddio voltage derating factor................................................................... 456 clock characteristics ..................................................................................... 457 master clock characteristics ....................................................................... 457 embedded flash characteristics ................................................................. 458 jtag/ice timings .......................................................................................... 459 ice interface signals ................................................................................... 459 jtag interface signals ................................................................................ 460
xiv at91sam7s64 preliminary 6070a?atarm?28-oct-04 at91sam7s64 mechanical characteristics .............................................. 462 thermal considerations................................................................................. 462 thermal data ............................................................................................... 462 junction temperature .................................................................................. 463 package drawings .......................................................................................... 463 soldering profile ............................................................................................. 465 at91sam7s64 ordering information............................................................ 466 table of contents i revision history ............................................................................................... xv
xv at91sam7s64 preliminary 6070a?atarm?28-oct-04 revision history doc. rev comments 6070a date: 28-oct-04
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